[PATCH] D76901: [AArch64][SVE] Add support for boolean logic and fcmp.

[Eli Friedman via Phabricator via llvm-commits]

efriedma marked 2 inline comments as done.
efriedma added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7563
+      if (ConstVal->isOne())
+        return getPTrue(DAG, dl, VT, AArch64SVEPredPattern::all);
+      // TODO: Add special case for constant false
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sdesmalen wrote:
> It seems like this code is missing a guard for `VT.isScalableVector()` (same for the `aarch64_sve_whilelo` case below)
Not sure what you think needs to be handled; non-scalable i1 vectors aren't legal.


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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:1369
   def : SVE_3_Op_Pat<nxv2i1, op, nxv2i1, nxv2i1, nxv2i1, !cast<Instruction>(NAME)>;
+  def : Pat<(nxv2i1 (op_nopred (nxv2i1 PPRAny:$Pn), (nxv2i1 PPRAny:$Pm))),
+            (!cast<Instruction>(NAME) (PTRUE_D 31), PPRAny:$Pn, PPRAny:$Pm)>;
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sdesmalen wrote:
> Do we want to create a `SVE_2_Op_<..>_Pat` or something for these? There will be other instructions where this would be useful as well.
> 
> nit: please reverse the order so it matches the patterns straight above it.
I'm not sure what that would look like.  Are you proposing something like SVE_2_Op_PTRUE_H_Pat/SVE_2_Op_PTRUE_S_Pat/etc.?


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  https://reviews.llvm.org/D76901/new/

https://reviews.llvm.org/D76901