[PATCH] D76740: [ARM] MVE VMULL patterns

[Sam Parker via Phabricator via llvm-commits]

samparker accepted this revision.
samparker added a comment.
This revision is now accepted and ready to land.

LGTM



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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:12166
+      return SDValue();
+    if (isAllOnesConstant(Mask->getOperand(0)) &&
+        isNullConstant(Mask->getOperand(1)) &&
----------------
dmgreen wrote:
> samparker wrote:
> > I'm a bit confused here... this looks like the AND mask is taking the 'top' parts of the elements, and if so, why don't we have to handle a 'bottom' element mask? Is this to do  with the revs I see in the isel patterns?
> I think this is bottom half? The 0 element is bottom half of the i64, 1 element would be top half of it.
> 
> And yes, the other pattern vmullt is the same pattern with some vrev's that we match in tablegen.
> 
> You reminded me that I did want to add some tests for both top and bottom at the same time.
Hmm, not sure how I misread that!


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Comment at: llvm/test/CodeGen/Thumb2/mve-vmull.ll:52
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vrev64.32 q2, q1
-; CHECK-NEXT:    vrev64.32 q1, q0
-; CHECK-NEXT:    vmov r0, s8
-; CHECK-NEXT:    vmov r1, s4
-; CHECK-NEXT:    umull r0, r1, r1, r0
-; CHECK-NEXT:    vmov.32 q0[0], r0
-; CHECK-NEXT:    vmov r0, s10
-; CHECK-NEXT:    vmov.32 q0[1], r1
-; CHECK-NEXT:    vmov r1, s6
-; CHECK-NEXT:    umull r0, r1, r1, r0
-; CHECK-NEXT:    vmov.32 q0[2], r0
-; CHECK-NEXT:    vmov.32 q0[3], r1
+; CHECK-NEXT:    vmullt.u32 q2, q0, q1
+; CHECK-NEXT:    vmov q0, q2
----------------
Do you know why we sometimes can't write to q0 too?


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  https://reviews.llvm.org/D76740/new/

https://reviews.llvm.org/D76740