[PATCH] D76740: [ARM] MVE VMULL patterns

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:12166
+      return SDValue();
+    if (isAllOnesConstant(Mask->getOperand(0)) &&
+        isNullConstant(Mask->getOperand(1)) &&
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samparker wrote:
> I'm a bit confused here... this looks like the AND mask is taking the 'top' parts of the elements, and if so, why don't we have to handle a 'bottom' element mask? Is this to do  with the revs I see in the isel patterns?
I think this is bottom half? The 0 element is bottom half of the i64, 1 element would be top half of it.

And yes, the other pattern vmullt is the same pattern with some vrev's that we match in tablegen.

You reminded me that I did want to add some tests for both top and bottom at the same time.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76740/new/

https://reviews.llvm.org/D76740