[PATCH] D76649: [X86] Move combineLoopMAddPattern and combineLoopSADPattern to an IR pass before SelecitonDAG.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 26 12:29:35 PDT 2020
craig.topper updated this revision to Diff 252935.
craig.topper added a comment.
Remove the vector reduction flag an associated SelectionDAGBuilder code
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D76649/new/
https://reviews.llvm.org/D76649
Files:
llvm/include/llvm/CodeGen/SelectionDAGNodes.h
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
llvm/lib/Target/X86/CMakeLists.txt
llvm/lib/Target/X86/X86.h
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86PartialReduction.cpp
llvm/lib/Target/X86/X86TargetMachine.cpp
llvm/test/CodeGen/X86/O3-pipeline.ll
llvm/test/CodeGen/X86/madd.ll
llvm/test/CodeGen/X86/min-legal-vector-width.ll
llvm/test/CodeGen/X86/sad.ll
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