[llvm] 5fc5c7d - Strength reduce vectors into arrays. NFCI.
David Blaikie via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 26 10:44:26 PDT 2020
Pity about the ones here where std::array was necessary rather than T t[] =
{...} - so the length had to be specified, rather than it being deduced
from the initializer length.
The first one, for instance - looking at ASTMatchers "hasAnyNameFunc" takes
an ArrayRef, but the old code passed a SmallVector - how did that work? &
how did the support for generalizing over std::array and SmallVector not
also generalize over a raw T[N]? I think ArrayRef is constructible from
T[N], but maybe some imperfect forwarding or something gets in the way?
(hmm, seems printOptionalAttrDict is ARrayRef too)
On Mon, Feb 17, 2020 at 6:38 AM Benjamin Kramer via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
>
> Author: Benjamin Kramer
> Date: 2020-02-17T15:37:35+01:00
> New Revision: 5fc5c7db38672c8962879b6fdce68393181c5e08
>
> URL:
> https://github.com/llvm/llvm-project/commit/5fc5c7db38672c8962879b6fdce68393181c5e08
> DIFF:
> https://github.com/llvm/llvm-project/commit/5fc5c7db38672c8962879b6fdce68393181c5e08.diff
>
> LOG: Strength reduce vectors into arrays. NFCI.
>
> Added:
>
>
> Modified:
>
> clang-tools-extra/clang-tidy/modernize/DeprecatedIosBaseAliasesCheck.cpp
> clang/lib/CodeGen/CGBuiltin.cpp
> clang/lib/Driver/ToolChains/Gnu.cpp
> clang/lib/Tooling/ArgumentsAdjusters.cpp
> llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
> llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
> llvm/lib/Target/ARM/ARMISelLowering.cpp
> llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
> llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
> llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
> llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
> mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp
> mlir/lib/Dialect/GPU/Transforms/AllReduceLowering.cpp
> mlir/lib/Dialect/StandardOps/Ops.cpp
> mlir/lib/Dialect/VectorOps/VectorOps.cpp
>
> Removed:
>
>
>
>
> ################################################################################
> diff --git
> a/clang-tools-extra/clang-tidy/modernize/DeprecatedIosBaseAliasesCheck.cpp
> b/clang-tools-extra/clang-tidy/modernize/DeprecatedIosBaseAliasesCheck.cpp
> index cd094219c50b..e00043841b99 100644
> ---
> a/clang-tools-extra/clang-tidy/modernize/DeprecatedIosBaseAliasesCheck.cpp
> +++
> b/clang-tools-extra/clang-tidy/modernize/DeprecatedIosBaseAliasesCheck.cpp
> @@ -16,12 +16,10 @@ namespace clang {
> namespace tidy {
> namespace modernize {
>
> -static const llvm::SmallVector<StringRef, 5> DeprecatedTypes = {
> - {"::std::ios_base::io_state"},
> - {"::std::ios_base::open_mode"},
> - {"::std::ios_base::seek_dir"},
> - {"::std::ios_base::streamoff"},
> - {"::std::ios_base::streampos"}};
> +static constexpr std::array<StringRef, 5> DeprecatedTypes = {
> + "::std::ios_base::io_state", "::std::ios_base::open_mode",
> + "::std::ios_base::seek_dir", "::std::ios_base::streamoff",
> + "::std::ios_base::streampos"};
>
> static const llvm::StringMap<StringRef> ReplacementTypes = {
> {"io_state", "iostate"},
>
> diff --git a/clang/lib/CodeGen/CGBuiltin.cpp
> b/clang/lib/CodeGen/CGBuiltin.cpp
> index 77f48b92eb01..af9be3a1c128 100644
> --- a/clang/lib/CodeGen/CGBuiltin.cpp
> +++ b/clang/lib/CodeGen/CGBuiltin.cpp
> @@ -3962,19 +3962,17 @@ RValue CodeGenFunction::EmitBuiltinExpr(const
> GlobalDecl GD, unsigned BuiltinID,
>
> // Create a vector of the arguments, as well as a constant value to
> // express to the runtime the number of variadic arguments.
> - std::vector<llvm::Value *> Args = {
> - Queue, Flags, Range,
> - Kernel, Block, ConstantInt::get(IntTy, NumArgs - 4),
> - ElemPtr};
> - std::vector<llvm::Type *> ArgTys = {
> + llvm::Value *const Args[] = {Queue, Flags,
> + Range, Kernel,
> + Block, ConstantInt::get(IntTy,
> NumArgs - 4),
> + ElemPtr};
> + llvm::Type *const ArgTys[] = {
> QueueTy, IntTy, RangeTy, GenericVoidPtrTy,
> GenericVoidPtrTy, IntTy, ElemPtr->getType()};
>
> - llvm::FunctionType *FTy = llvm::FunctionType::get(
> - Int32Ty, llvm::ArrayRef<llvm::Type *>(ArgTys), false);
> - auto Call =
> - RValue::get(Builder.CreateCall(CGM.CreateRuntimeFunction(FTy,
> Name),
> - llvm::ArrayRef<llvm::Value
> *>(Args)));
> + llvm::FunctionType *FTy = llvm::FunctionType::get(Int32Ty, ArgTys,
> false);
> + auto Call = RValue::get(
> + Builder.CreateCall(CGM.CreateRuntimeFunction(FTy, Name), Args));
> if (TmpSize)
> EmitLifetimeEnd(TmpSize, TmpPtr);
> return Call;
>
> diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp
> b/clang/lib/Driver/ToolChains/Gnu.cpp
> index 2652c05d844f..c356657541fa 100644
> --- a/clang/lib/Driver/ToolChains/Gnu.cpp
> +++ b/clang/lib/Driver/ToolChains/Gnu.cpp
> @@ -1527,7 +1527,7 @@ static void findRISCVBareMetalMultilibs(const Driver
> &D,
> };
> // currently only support the set of multilibs like riscv-gnu-toolchain
> does.
> // TODO: support MULTILIB_REUSE
> - SmallVector<RiscvMultilib, 8> RISCVMultilibSet = {
> + constexpr RiscvMultilib RISCVMultilibSet[] = {
> {"rv32i", "ilp32"}, {"rv32im", "ilp32"}, {"rv32iac",
> "ilp32"},
> {"rv32imac", "ilp32"}, {"rv32imafc", "ilp32f"}, {"rv64imac",
> "lp64"},
> {"rv64imafdc", "lp64d"}};
>
> diff --git a/clang/lib/Tooling/ArgumentsAdjusters.cpp
> b/clang/lib/Tooling/ArgumentsAdjusters.cpp
> index a609e4ed2469..5869377a03c9 100644
> --- a/clang/lib/Tooling/ArgumentsAdjusters.cpp
> +++ b/clang/lib/Tooling/ArgumentsAdjusters.cpp
> @@ -26,7 +26,7 @@ ArgumentsAdjuster getClangSyntaxOnlyAdjuster() {
> return [](const CommandLineArguments &Args, StringRef /*unused*/) {
> CommandLineArguments AdjustedArgs;
> bool HasSyntaxOnly = false;
> - const std::vector<llvm::StringRef> OutputCommands = {
> + constexpr llvm::StringRef OutputCommands[] = {
> // FIXME: Add other options that generate output.
> "-save-temps",
> "--save-temps",
>
> diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
> b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
> index 540a6235e15d..8e9c2337e938 100644
> --- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
> +++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
> @@ -4205,7 +4205,7 @@ static void writeIdentificationBlock(BitstreamWriter
> &Stream) {
> Abbv->Add(BitCodeAbbrevOp(bitc::IDENTIFICATION_CODE_EPOCH));
> Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));
> auto EpochAbbrev = Stream.EmitAbbrev(std::move(Abbv));
> - SmallVector<unsigned, 1> Vals = {bitc::BITCODE_CURRENT_EPOCH};
> + constexpr std::array<unsigned, 1> Vals = {bitc::BITCODE_CURRENT_EPOCH};
> Stream.EmitRecord(bitc::IDENTIFICATION_CODE_EPOCH, Vals, EpochAbbrev);
> Stream.ExitBlock();
> }
>
> diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
> b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
> index fa2b52df27bf..eb4215b49075 100644
> --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
> +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
> @@ -3288,7 +3288,6 @@ SDValue
> DAGTypeLegalizer::WidenVecRes_Convert_StrictFP(SDNode *N) {
>
> EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),
> N->getValueType(0));
> unsigned WidenNumElts = WidenVT.getVectorNumElements();
> - SmallVector<EVT, 2> WidenVTs = { WidenVT, MVT::Other };
>
> EVT InVT = InOp.getValueType();
> EVT InEltVT = InVT.getVectorElementType();
> @@ -3299,7 +3298,7 @@ SDValue
> DAGTypeLegalizer::WidenVecRes_Convert_StrictFP(SDNode *N) {
>
> // Otherwise unroll into some nasty scalar code and rebuild the vector.
> EVT EltVT = WidenVT.getVectorElementType();
> - SmallVector<EVT, 2> EltVTs = { EltVT, MVT::Other };
> + std::array<EVT, 2> EltVTs = {EltVT, MVT::Other};
> SmallVector<SDValue, 16> Ops(WidenNumElts, DAG.getUNDEF(EltVT));
> SmallVector<SDValue, 32> OpChains;
> // Use the original element count so we don't do more scalar opts than
>
> diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp
> b/llvm/lib/Target/ARM/ARMISelLowering.cpp
> index 5c01ac1abdcc..76d4ffa466b2 100644
> --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
> +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
> @@ -3637,7 +3637,7 @@ SDValue ARMTargetLowering::LowerINTRINSIC_VOID(
> unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
> SDValue ReturnAddress =
> DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, PtrVT);
> - std::vector<EVT> ResultTys = {MVT::Other, MVT::Glue};
> + constexpr EVT ResultTys[] = {MVT::Other, MVT::Glue};
> SDValue Callee =
> DAG.getTargetExternalSymbol("\01__gnu_mcount_nc", PtrVT, 0);
> SDValue RegisterMask = DAG.getRegisterMask(Mask);
>
> diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
> b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
> index 7e143a349400..361c3388276a 100644
> --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
> +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp
> @@ -2201,29 +2201,29 @@ void
> HexagonDAGToDAGISel::SelectHVXDualOutput(SDNode *N) {
> SDNode *Result;
> switch (IID) {
> case Intrinsic::hexagon_V6_vaddcarry: {
> - SmallVector<SDValue, 3> Ops = { N->getOperand(1), N->getOperand(2),
> - N->getOperand(3) };
> + std::array<SDValue, 3> Ops = {N->getOperand(1), N->getOperand(2),
> + N->getOperand(3)};
> SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v512i1);
> Result = CurDAG->getMachineNode(Hexagon::V6_vaddcarry, SDLoc(N), VTs,
> Ops);
> break;
> }
> case Intrinsic::hexagon_V6_vaddcarry_128B: {
> - SmallVector<SDValue, 3> Ops = { N->getOperand(1), N->getOperand(2),
> - N->getOperand(3) };
> + std::array<SDValue, 3> Ops = {N->getOperand(1), N->getOperand(2),
> + N->getOperand(3)};
> SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v1024i1);
> Result = CurDAG->getMachineNode(Hexagon::V6_vaddcarry, SDLoc(N), VTs,
> Ops);
> break;
> }
> case Intrinsic::hexagon_V6_vsubcarry: {
> - SmallVector<SDValue, 3> Ops = { N->getOperand(1), N->getOperand(2),
> - N->getOperand(3) };
> + std::array<SDValue, 3> Ops = {N->getOperand(1), N->getOperand(2),
> + N->getOperand(3)};
> SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v512i1);
> Result = CurDAG->getMachineNode(Hexagon::V6_vsubcarry, SDLoc(N), VTs,
> Ops);
> break;
> }
> case Intrinsic::hexagon_V6_vsubcarry_128B: {
> - SmallVector<SDValue, 3> Ops = { N->getOperand(1), N->getOperand(2),
> - N->getOperand(3) };
> + std::array<SDValue, 3> Ops = {N->getOperand(1), N->getOperand(2),
> + N->getOperand(3)};
> SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v1024i1);
> Result = CurDAG->getMachineNode(Hexagon::V6_vsubcarry, SDLoc(N), VTs,
> Ops);
> break;
>
> diff --git a/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
> b/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
> index db93b3d80ede..d48672218480 100644
> --- a/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
> +++ b/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp
> @@ -376,7 +376,7 @@ static bool CheckXWPInstr(MachineInstr *MI, bool
> ReduceToLwp,
>
> // Returns true if the registers Reg1 and Reg2 are consecutive
> static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) {
> - static SmallVector<unsigned, 31> Registers = {
> + constexpr std::array<unsigned, 31> Registers = {
> Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2,
> Mips::A3,
> Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5,
> Mips::T6,
> Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4,
> Mips::S5,
>
> diff --git
> a/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
> b/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
> index 689922bb37b9..39aecc7c463b 100644
> --- a/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
> +++ b/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp
> @@ -688,9 +688,9 @@ bool
> WebAssemblyLowerEmscriptenEHSjLj::runOnModule(Module &M) {
> if (SetjmpF) {
> // Register saveSetjmp function
> FunctionType *SetjmpFTy = SetjmpF->getFunctionType();
> - SmallVector<Type *, 4> Params = {SetjmpFTy->getParamType(0),
> - IRB.getInt32Ty(),
> Type::getInt32PtrTy(C),
> - IRB.getInt32Ty()};
> + std::array<Type *, 4> Params = {SetjmpFTy->getParamType(0),
> + IRB.getInt32Ty(),
> Type::getInt32PtrTy(C),
> + IRB.getInt32Ty()};
> FunctionType *FTy =
> FunctionType::get(Type::getInt32PtrTy(C), Params, false);
> SaveSetjmpF =
>
> diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
> b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
> index 2a78628e75e2..91aeb33fb2d2 100644
> --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
> +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
> @@ -868,7 +868,7 @@ class BoUpSLP {
> int getExternalUsesCost(const std::pair<Value *, int> &LHS,
> const std::pair<Value *, int> &RHS) {
> int Cost = 0;
> - SmallVector<std::pair<Value *, int>, 2> Values = {LHS, RHS};
> + std::array<std::pair<Value *, int>, 2> Values = {LHS, RHS};
> for (int Idx = 0, IdxE = Values.size(); Idx != IdxE; ++Idx) {
> Value *V = Values[Idx].first;
> // Calculate the absolute lane, using the minimum relative lane
> of LHS
>
> diff --git a/mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp
> b/mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp
> index b92bcf7bc2ae..bf3dfb5a2843 100644
> --- a/mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp
> +++ b/mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp
> @@ -294,8 +294,8 @@ static void packIdAndNumId(gpu::KernelDim3 kernelIds,
> SmallVectorImpl<Value> &ids,
> SmallVectorImpl<Value> &nids) {
> assert(nDims <= 3 && "invalid number of launch dimensions");
> - SmallVector<Value, 3> allIds = {kernelIds.z, kernelIds.y, kernelIds.x};
> - SmallVector<Value, 3> allNids = {kernelNids.z, kernelNids.y,
> kernelNids.x};
> + std::array<Value, 3> allIds = {kernelIds.z, kernelIds.y, kernelIds.x};
> + std::array<Value, 3> allNids = {kernelNids.z, kernelNids.y,
> kernelNids.x};
> ids.clear();
> ids.append(std::next(allIds.begin(), allIds.size() - nDims),
> allIds.end());
> nids.clear();
> @@ -814,4 +814,4 @@ void ParallelLoopToGpuPass::runOnOperation() {
>
> static PassRegistration<ParallelLoopToGpuPass>
> pass("convert-parallel-loops-to-gpu", "Convert mapped loop.parallel
> ops"
> - " to gpu launch operations.");
> \ No newline at end of file
> + " to gpu launch operations.");
>
> diff --git a/mlir/lib/Dialect/GPU/Transforms/AllReduceLowering.cpp
> b/mlir/lib/Dialect/GPU/Transforms/AllReduceLowering.cpp
> index 752debad163c..3b478dd0a197 100644
> --- a/mlir/lib/Dialect/GPU/Transforms/AllReduceLowering.cpp
> +++ b/mlir/lib/Dialect/GPU/Transforms/AllReduceLowering.cpp
> @@ -285,7 +285,7 @@ struct GpuAllReduceRewriter {
> Value subgroupSize = create<ConstantIntOp>(kSubgroupSize, int32Type);
> Value isPartialSubgroup =
> create<CmpIOp>(CmpIPredicate::slt, activeWidth, subgroupSize);
> - SmallVector<Type, 2> shuffleType = {valueType, rewriter.getI1Type()};
> + std::array<Type, 2> shuffleType = {valueType, rewriter.getI1Type()};
> auto xorAttr = rewriter.getStringAttr("xor");
>
> createIf(
>
> diff --git a/mlir/lib/Dialect/StandardOps/Ops.cpp
> b/mlir/lib/Dialect/StandardOps/Ops.cpp
> index 0b58fb73e91d..81f5d4a153f6 100644
> --- a/mlir/lib/Dialect/StandardOps/Ops.cpp
> +++ b/mlir/lib/Dialect/StandardOps/Ops.cpp
> @@ -1948,7 +1948,7 @@ static ParseResult parseSelectOp(OpAsmParser
> &parser, OperationState &result) {
> return parser.emitError(parser.getNameLoc(),
> "expected type with valid i1 shape");
>
> - SmallVector<Type, 3> types = {i1Type, type, type};
> + std::array<Type, 3> types = {i1Type, type, type};
> return failure(parser.resolveOperands(ops, types, parser.getNameLoc(),
> result.operands) ||
> parser.addTypeToList(type, result.types));
> @@ -2597,7 +2597,7 @@ static void print(OpAsmPrinter &p, SubViewOp op) {
> p << op.getOperationName() << ' ' << op.getOperand(0) << '[' <<
> op.offsets()
> << "][" << op.sizes() << "][" << op.strides() << ']';
>
> - SmallVector<StringRef, 1> elidedAttrs = {
> + std::array<StringRef, 1> elidedAttrs = {
> SubViewOp::getOperandSegmentSizeAttr()};
> p.printOptionalAttrDict(op.getAttrs(), elidedAttrs);
> p << " : " << op.getOperand(0).getType() << " to " << op.getType();
>
> diff --git a/mlir/lib/Dialect/VectorOps/VectorOps.cpp
> b/mlir/lib/Dialect/VectorOps/VectorOps.cpp
> index 174efb66ccd4..27623f113f1e 100644
> --- a/mlir/lib/Dialect/VectorOps/VectorOps.cpp
> +++ b/mlir/lib/Dialect/VectorOps/VectorOps.cpp
> @@ -1018,7 +1018,7 @@ static LogicalResult verify(OuterProductOp op) {
> static void print(OpAsmPrinter &p, ReshapeOp op) {
> p << op.getOperationName() << " " << op.vector() << ", [" <<
> op.input_shape()
> << "], [" << op.output_shape() << "], " << op.fixed_vector_sizes();
> - SmallVector<StringRef, 2> elidedAttrs = {
> + std::array<StringRef, 2> elidedAttrs = {
> ReshapeOp::getOperandSegmentSizeAttr(),
> ReshapeOp::getFixedVectorSizesAttrName()};
> p.printOptionalAttrDict(op.getAttrs(), elidedAttrs);
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at lists.llvm.org
> https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200326/252a0c56/attachment-0001.html>
More information about the llvm-commits
mailing list