<div dir="ltr">Pity about the ones here where std::array was necessary rather than T t[] = {...} - so the length had to be specified, rather than it being deduced from the initializer length.<br><br>The first one, for instance - looking at ASTMatchers "hasAnyNameFunc" takes an ArrayRef, but the old code passed a SmallVector - how did that work? & how did the support for generalizing over std::array and SmallVector not also generalize over a raw T[N]? I think ArrayRef is constructible from T[N], but maybe some imperfect forwarding or something gets in the way? (hmm, seems printOptionalAttrDict is ARrayRef too)</div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Mon, Feb 17, 2020 at 6:38 AM Benjamin Kramer via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
Author: Benjamin Kramer<br>
Date: 2020-02-17T15:37:35+01:00<br>
New Revision: 5fc5c7db38672c8962879b6fdce68393181c5e08<br>
<br>
URL: <a href="https://github.com/llvm/llvm-project/commit/5fc5c7db38672c8962879b6fdce68393181c5e08" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/5fc5c7db38672c8962879b6fdce68393181c5e08</a><br>
DIFF: <a href="https://github.com/llvm/llvm-project/commit/5fc5c7db38672c8962879b6fdce68393181c5e08.diff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/5fc5c7db38672c8962879b6fdce68393181c5e08.diff</a><br>
<br>
LOG: Strength reduce vectors into arrays. NFCI.<br>
<br>
Added: <br>
<br>
<br>
Modified: <br>
clang-tools-extra/clang-tidy/modernize/DeprecatedIosBaseAliasesCheck.cpp<br>
clang/lib/CodeGen/CGBuiltin.cpp<br>
clang/lib/Driver/ToolChains/Gnu.cpp<br>
clang/lib/Tooling/ArgumentsAdjusters.cpp<br>
llvm/lib/Bitcode/Writer/BitcodeWriter.cpp<br>
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br>
llvm/lib/Target/ARM/ARMISelLowering.cpp<br>
llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp<br>
llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp<br>
llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp<br>
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp<br>
mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp<br>
mlir/lib/Dialect/GPU/Transforms/AllReduceLowering.cpp<br>
mlir/lib/Dialect/StandardOps/Ops.cpp<br>
mlir/lib/Dialect/VectorOps/VectorOps.cpp<br>
<br>
Removed: <br>
<br>
<br>
<br>
################################################################################<br>
diff --git a/clang-tools-extra/clang-tidy/modernize/DeprecatedIosBaseAliasesCheck.cpp b/clang-tools-extra/clang-tidy/modernize/DeprecatedIosBaseAliasesCheck.cpp<br>
index cd094219c50b..e00043841b99 100644<br>
--- a/clang-tools-extra/clang-tidy/modernize/DeprecatedIosBaseAliasesCheck.cpp<br>
+++ b/clang-tools-extra/clang-tidy/modernize/DeprecatedIosBaseAliasesCheck.cpp<br>
@@ -16,12 +16,10 @@ namespace clang {<br>
namespace tidy {<br>
namespace modernize {<br>
<br>
-static const llvm::SmallVector<StringRef, 5> DeprecatedTypes = {<br>
- {"::std::ios_base::io_state"},<br>
- {"::std::ios_base::open_mode"},<br>
- {"::std::ios_base::seek_dir"},<br>
- {"::std::ios_base::streamoff"},<br>
- {"::std::ios_base::streampos"}};<br>
+static constexpr std::array<StringRef, 5> DeprecatedTypes = {<br>
+ "::std::ios_base::io_state", "::std::ios_base::open_mode",<br>
+ "::std::ios_base::seek_dir", "::std::ios_base::streamoff",<br>
+ "::std::ios_base::streampos"};<br>
<br>
static const llvm::StringMap<StringRef> ReplacementTypes = {<br>
{"io_state", "iostate"},<br>
<br>
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp<br>
index 77f48b92eb01..af9be3a1c128 100644<br>
--- a/clang/lib/CodeGen/CGBuiltin.cpp<br>
+++ b/clang/lib/CodeGen/CGBuiltin.cpp<br>
@@ -3962,19 +3962,17 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,<br>
<br>
// Create a vector of the arguments, as well as a constant value to<br>
// express to the runtime the number of variadic arguments.<br>
- std::vector<llvm::Value *> Args = {<br>
- Queue, Flags, Range,<br>
- Kernel, Block, ConstantInt::get(IntTy, NumArgs - 4),<br>
- ElemPtr};<br>
- std::vector<llvm::Type *> ArgTys = {<br>
+ llvm::Value *const Args[] = {Queue, Flags,<br>
+ Range, Kernel,<br>
+ Block, ConstantInt::get(IntTy, NumArgs - 4),<br>
+ ElemPtr};<br>
+ llvm::Type *const ArgTys[] = {<br>
QueueTy, IntTy, RangeTy, GenericVoidPtrTy,<br>
GenericVoidPtrTy, IntTy, ElemPtr->getType()};<br>
<br>
- llvm::FunctionType *FTy = llvm::FunctionType::get(<br>
- Int32Ty, llvm::ArrayRef<llvm::Type *>(ArgTys), false);<br>
- auto Call =<br>
- RValue::get(Builder.CreateCall(CGM.CreateRuntimeFunction(FTy, Name),<br>
- llvm::ArrayRef<llvm::Value *>(Args)));<br>
+ llvm::FunctionType *FTy = llvm::FunctionType::get(Int32Ty, ArgTys, false);<br>
+ auto Call = RValue::get(<br>
+ Builder.CreateCall(CGM.CreateRuntimeFunction(FTy, Name), Args));<br>
if (TmpSize)<br>
EmitLifetimeEnd(TmpSize, TmpPtr);<br>
return Call;<br>
<br>
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp<br>
index 2652c05d844f..c356657541fa 100644<br>
--- a/clang/lib/Driver/ToolChains/Gnu.cpp<br>
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp<br>
@@ -1527,7 +1527,7 @@ static void findRISCVBareMetalMultilibs(const Driver &D,<br>
};<br>
// currently only support the set of multilibs like riscv-gnu-toolchain does.<br>
// TODO: support MULTILIB_REUSE<br>
- SmallVector<RiscvMultilib, 8> RISCVMultilibSet = {<br>
+ constexpr RiscvMultilib RISCVMultilibSet[] = {<br>
{"rv32i", "ilp32"}, {"rv32im", "ilp32"}, {"rv32iac", "ilp32"},<br>
{"rv32imac", "ilp32"}, {"rv32imafc", "ilp32f"}, {"rv64imac", "lp64"},<br>
{"rv64imafdc", "lp64d"}};<br>
<br>
diff --git a/clang/lib/Tooling/ArgumentsAdjusters.cpp b/clang/lib/Tooling/ArgumentsAdjusters.cpp<br>
index a609e4ed2469..5869377a03c9 100644<br>
--- a/clang/lib/Tooling/ArgumentsAdjusters.cpp<br>
+++ b/clang/lib/Tooling/ArgumentsAdjusters.cpp<br>
@@ -26,7 +26,7 @@ ArgumentsAdjuster getClangSyntaxOnlyAdjuster() {<br>
return [](const CommandLineArguments &Args, StringRef /*unused*/) {<br>
CommandLineArguments AdjustedArgs;<br>
bool HasSyntaxOnly = false;<br>
- const std::vector<llvm::StringRef> OutputCommands = {<br>
+ constexpr llvm::StringRef OutputCommands[] = {<br>
// FIXME: Add other options that generate output.<br>
"-save-temps",<br>
"--save-temps",<br>
<br>
diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp<br>
index 540a6235e15d..8e9c2337e938 100644<br>
--- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp<br>
+++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp<br>
@@ -4205,7 +4205,7 @@ static void writeIdentificationBlock(BitstreamWriter &Stream) {<br>
Abbv->Add(BitCodeAbbrevOp(bitc::IDENTIFICATION_CODE_EPOCH));<br>
Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::VBR, 6));<br>
auto EpochAbbrev = Stream.EmitAbbrev(std::move(Abbv));<br>
- SmallVector<unsigned, 1> Vals = {bitc::BITCODE_CURRENT_EPOCH};<br>
+ constexpr std::array<unsigned, 1> Vals = {bitc::BITCODE_CURRENT_EPOCH};<br>
Stream.EmitRecord(bitc::IDENTIFICATION_CODE_EPOCH, Vals, EpochAbbrev);<br>
Stream.ExitBlock();<br>
}<br>
<br>
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br>
index fa2b52df27bf..eb4215b49075 100644<br>
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br>
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br>
@@ -3288,7 +3288,6 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert_StrictFP(SDNode *N) {<br>
<br>
EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));<br>
unsigned WidenNumElts = WidenVT.getVectorNumElements();<br>
- SmallVector<EVT, 2> WidenVTs = { WidenVT, MVT::Other };<br>
<br>
EVT InVT = InOp.getValueType();<br>
EVT InEltVT = InVT.getVectorElementType();<br>
@@ -3299,7 +3298,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert_StrictFP(SDNode *N) {<br>
<br>
// Otherwise unroll into some nasty scalar code and rebuild the vector.<br>
EVT EltVT = WidenVT.getVectorElementType();<br>
- SmallVector<EVT, 2> EltVTs = { EltVT, MVT::Other };<br>
+ std::array<EVT, 2> EltVTs = {EltVT, MVT::Other};<br>
SmallVector<SDValue, 16> Ops(WidenNumElts, DAG.getUNDEF(EltVT));<br>
SmallVector<SDValue, 32> OpChains;<br>
// Use the original element count so we don't do more scalar opts than<br>
<br>
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp<br>
index 5c01ac1abdcc..76d4ffa466b2 100644<br>
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp<br>
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp<br>
@@ -3637,7 +3637,7 @@ SDValue ARMTargetLowering::LowerINTRINSIC_VOID(<br>
unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));<br>
SDValue ReturnAddress =<br>
DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, PtrVT);<br>
- std::vector<EVT> ResultTys = {MVT::Other, MVT::Glue};<br>
+ constexpr EVT ResultTys[] = {MVT::Other, MVT::Glue};<br>
SDValue Callee =<br>
DAG.getTargetExternalSymbol("\01__gnu_mcount_nc", PtrVT, 0);<br>
SDValue RegisterMask = DAG.getRegisterMask(Mask);<br>
<br>
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp<br>
index 7e143a349400..361c3388276a 100644<br>
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp<br>
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp<br>
@@ -2201,29 +2201,29 @@ void HexagonDAGToDAGISel::SelectHVXDualOutput(SDNode *N) {<br>
SDNode *Result;<br>
switch (IID) {<br>
case Intrinsic::hexagon_V6_vaddcarry: {<br>
- SmallVector<SDValue, 3> Ops = { N->getOperand(1), N->getOperand(2),<br>
- N->getOperand(3) };<br>
+ std::array<SDValue, 3> Ops = {N->getOperand(1), N->getOperand(2),<br>
+ N->getOperand(3)};<br>
SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v512i1);<br>
Result = CurDAG->getMachineNode(Hexagon::V6_vaddcarry, SDLoc(N), VTs, Ops);<br>
break;<br>
}<br>
case Intrinsic::hexagon_V6_vaddcarry_128B: {<br>
- SmallVector<SDValue, 3> Ops = { N->getOperand(1), N->getOperand(2),<br>
- N->getOperand(3) };<br>
+ std::array<SDValue, 3> Ops = {N->getOperand(1), N->getOperand(2),<br>
+ N->getOperand(3)};<br>
SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v1024i1);<br>
Result = CurDAG->getMachineNode(Hexagon::V6_vaddcarry, SDLoc(N), VTs, Ops);<br>
break;<br>
}<br>
case Intrinsic::hexagon_V6_vsubcarry: {<br>
- SmallVector<SDValue, 3> Ops = { N->getOperand(1), N->getOperand(2),<br>
- N->getOperand(3) };<br>
+ std::array<SDValue, 3> Ops = {N->getOperand(1), N->getOperand(2),<br>
+ N->getOperand(3)};<br>
SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v512i1);<br>
Result = CurDAG->getMachineNode(Hexagon::V6_vsubcarry, SDLoc(N), VTs, Ops);<br>
break;<br>
}<br>
case Intrinsic::hexagon_V6_vsubcarry_128B: {<br>
- SmallVector<SDValue, 3> Ops = { N->getOperand(1), N->getOperand(2),<br>
- N->getOperand(3) };<br>
+ std::array<SDValue, 3> Ops = {N->getOperand(1), N->getOperand(2),<br>
+ N->getOperand(3)};<br>
SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v1024i1);<br>
Result = CurDAG->getMachineNode(Hexagon::V6_vsubcarry, SDLoc(N), VTs, Ops);<br>
break;<br>
<br>
diff --git a/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp b/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp<br>
index db93b3d80ede..d48672218480 100644<br>
--- a/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp<br>
+++ b/llvm/lib/Target/Mips/MicroMipsSizeReduction.cpp<br>
@@ -376,7 +376,7 @@ static bool CheckXWPInstr(MachineInstr *MI, bool ReduceToLwp,<br>
<br>
// Returns true if the registers Reg1 and Reg2 are consecutive<br>
static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) {<br>
- static SmallVector<unsigned, 31> Registers = {<br>
+ constexpr std::array<unsigned, 31> Registers = {<br>
Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3,<br>
Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6,<br>
Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,<br>
<br>
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp<br>
index 689922bb37b9..39aecc7c463b 100644<br>
--- a/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp<br>
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyLowerEmscriptenEHSjLj.cpp<br>
@@ -688,9 +688,9 @@ bool WebAssemblyLowerEmscriptenEHSjLj::runOnModule(Module &M) {<br>
if (SetjmpF) {<br>
// Register saveSetjmp function<br>
FunctionType *SetjmpFTy = SetjmpF->getFunctionType();<br>
- SmallVector<Type *, 4> Params = {SetjmpFTy->getParamType(0),<br>
- IRB.getInt32Ty(), Type::getInt32PtrTy(C),<br>
- IRB.getInt32Ty()};<br>
+ std::array<Type *, 4> Params = {SetjmpFTy->getParamType(0),<br>
+ IRB.getInt32Ty(), Type::getInt32PtrTy(C),<br>
+ IRB.getInt32Ty()};<br>
FunctionType *FTy =<br>
FunctionType::get(Type::getInt32PtrTy(C), Params, false);<br>
SaveSetjmpF =<br>
<br>
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp<br>
index 2a78628e75e2..91aeb33fb2d2 100644<br>
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp<br>
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp<br>
@@ -868,7 +868,7 @@ class BoUpSLP {<br>
int getExternalUsesCost(const std::pair<Value *, int> &LHS,<br>
const std::pair<Value *, int> &RHS) {<br>
int Cost = 0;<br>
- SmallVector<std::pair<Value *, int>, 2> Values = {LHS, RHS};<br>
+ std::array<std::pair<Value *, int>, 2> Values = {LHS, RHS};<br>
for (int Idx = 0, IdxE = Values.size(); Idx != IdxE; ++Idx) {<br>
Value *V = Values[Idx].first;<br>
// Calculate the absolute lane, using the minimum relative lane of LHS<br>
<br>
diff --git a/mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp b/mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp<br>
index b92bcf7bc2ae..bf3dfb5a2843 100644<br>
--- a/mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp<br>
+++ b/mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp<br>
@@ -294,8 +294,8 @@ static void packIdAndNumId(gpu::KernelDim3 kernelIds,<br>
SmallVectorImpl<Value> &ids,<br>
SmallVectorImpl<Value> &nids) {<br>
assert(nDims <= 3 && "invalid number of launch dimensions");<br>
- SmallVector<Value, 3> allIds = {kernelIds.z, kernelIds.y, kernelIds.x};<br>
- SmallVector<Value, 3> allNids = {kernelNids.z, kernelNids.y, kernelNids.x};<br>
+ std::array<Value, 3> allIds = {kernelIds.z, kernelIds.y, kernelIds.x};<br>
+ std::array<Value, 3> allNids = {kernelNids.z, kernelNids.y, kernelNids.x};<br>
ids.clear();<br>
ids.append(std::next(allIds.begin(), allIds.size() - nDims), allIds.end());<br>
nids.clear();<br>
@@ -814,4 +814,4 @@ void ParallelLoopToGpuPass::runOnOperation() {<br>
<br>
static PassRegistration<ParallelLoopToGpuPass><br>
pass("convert-parallel-loops-to-gpu", "Convert mapped loop.parallel ops"<br>
- " to gpu launch operations.");<br>
\ No newline at end of file<br>
+ " to gpu launch operations.");<br>
<br>
diff --git a/mlir/lib/Dialect/GPU/Transforms/AllReduceLowering.cpp b/mlir/lib/Dialect/GPU/Transforms/AllReduceLowering.cpp<br>
index 752debad163c..3b478dd0a197 100644<br>
--- a/mlir/lib/Dialect/GPU/Transforms/AllReduceLowering.cpp<br>
+++ b/mlir/lib/Dialect/GPU/Transforms/AllReduceLowering.cpp<br>
@@ -285,7 +285,7 @@ struct GpuAllReduceRewriter {<br>
Value subgroupSize = create<ConstantIntOp>(kSubgroupSize, int32Type);<br>
Value isPartialSubgroup =<br>
create<CmpIOp>(CmpIPredicate::slt, activeWidth, subgroupSize);<br>
- SmallVector<Type, 2> shuffleType = {valueType, rewriter.getI1Type()};<br>
+ std::array<Type, 2> shuffleType = {valueType, rewriter.getI1Type()};<br>
auto xorAttr = rewriter.getStringAttr("xor");<br>
<br>
createIf(<br>
<br>
diff --git a/mlir/lib/Dialect/StandardOps/Ops.cpp b/mlir/lib/Dialect/StandardOps/Ops.cpp<br>
index 0b58fb73e91d..81f5d4a153f6 100644<br>
--- a/mlir/lib/Dialect/StandardOps/Ops.cpp<br>
+++ b/mlir/lib/Dialect/StandardOps/Ops.cpp<br>
@@ -1948,7 +1948,7 @@ static ParseResult parseSelectOp(OpAsmParser &parser, OperationState &result) {<br>
return parser.emitError(parser.getNameLoc(),<br>
"expected type with valid i1 shape");<br>
<br>
- SmallVector<Type, 3> types = {i1Type, type, type};<br>
+ std::array<Type, 3> types = {i1Type, type, type};<br>
return failure(parser.resolveOperands(ops, types, parser.getNameLoc(),<br>
result.operands) ||<br>
parser.addTypeToList(type, result.types));<br>
@@ -2597,7 +2597,7 @@ static void print(OpAsmPrinter &p, SubViewOp op) {<br>
p << op.getOperationName() << ' ' << op.getOperand(0) << '[' << op.offsets()<br>
<< "][" << op.sizes() << "][" << op.strides() << ']';<br>
<br>
- SmallVector<StringRef, 1> elidedAttrs = {<br>
+ std::array<StringRef, 1> elidedAttrs = {<br>
SubViewOp::getOperandSegmentSizeAttr()};<br>
p.printOptionalAttrDict(op.getAttrs(), elidedAttrs);<br>
p << " : " << op.getOperand(0).getType() << " to " << op.getType();<br>
<br>
diff --git a/mlir/lib/Dialect/VectorOps/VectorOps.cpp b/mlir/lib/Dialect/VectorOps/VectorOps.cpp<br>
index 174efb66ccd4..27623f113f1e 100644<br>
--- a/mlir/lib/Dialect/VectorOps/VectorOps.cpp<br>
+++ b/mlir/lib/Dialect/VectorOps/VectorOps.cpp<br>
@@ -1018,7 +1018,7 @@ static LogicalResult verify(OuterProductOp op) {<br>
static void print(OpAsmPrinter &p, ReshapeOp op) {<br>
p << op.getOperationName() << " " << op.vector() << ", [" << op.input_shape()<br>
<< "], [" << op.output_shape() << "], " << op.fixed_vector_sizes();<br>
- SmallVector<StringRef, 2> elidedAttrs = {<br>
+ std::array<StringRef, 2> elidedAttrs = {<br>
ReshapeOp::getOperandSegmentSizeAttr(),<br>
ReshapeOp::getFixedVectorSizesAttrName()};<br>
p.printOptionalAttrDict(op.getAttrs(), elidedAttrs);<br>
<br>
<br>
<br>
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</blockquote></div>