[PATCH] D76649: [X86] Move combineLoopMAddPattern and combineLoopSADPattern to an IR pass before SelecitonDAG.

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

There's still 1 other use of the flag in DAGCombiner IIUC, but if we can find a way to get rid of that too, that would be great.



================
Comment at: llvm/lib/Target/X86/X86PartialReduction.cpp:69
+
+static bool isVectorReductionOp(const BinaryOperator &BO) {
+  if (!BO.getType()->isVectorTy())
----------------
Is this identical to the existing code in SelectionDAGBuilder? Could we hoist that to VectorUtils.cpp, so we don't have duplicate code?


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  https://reviews.llvm.org/D76649/new/

https://reviews.llvm.org/D76649