[llvm] 146df55 - [X86][AVX] Add common prefix to merge 32/64-bit AVX1 checks
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 25 08:34:59 PDT 2020
Author: Simon Pilgrim
Date: 2020-03-25T15:33:58Z
New Revision: 146df5581d9825505f6a4fef976842a1f36bdeb2
URL: https://github.com/llvm/llvm-project/commit/146df5581d9825505f6a4fef976842a1f36bdeb2
DIFF: https://github.com/llvm/llvm-project/commit/146df5581d9825505f6a4fef976842a1f36bdeb2.diff
LOG: [X86][AVX] Add common prefix to merge 32/64-bit AVX1 checks
Added:
Modified:
llvm/test/CodeGen/X86/vec-strict-fptoint-256.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/vec-strict-fptoint-256.ll b/llvm/test/CodeGen/X86/vec-strict-fptoint-256.ll
index 38f19e9ed2d5..9c704b1d526f 100644
--- a/llvm/test/CodeGen/X86/vec-strict-fptoint-256.ll
+++ b/llvm/test/CodeGen/X86/vec-strict-fptoint-256.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=CHECK,AVX-32
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=CHECK,AVX-64
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=CHECK,AVX,AVX-32
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=CHECK,AVX,AVX-64
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512f -O3 | FileCheck %s --check-prefixes=CHECK,AVX512F,AVX512F-32
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f -O3 | FileCheck %s --check-prefixes=CHECK,AVX512F,AVX512F-64
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vl -O3 | FileCheck %s --check-prefixes=CHECK,AVX512VL,AVX512VL-32
@@ -1173,39 +1173,22 @@ define <4 x i32> @strict_vector_fptosi_v4f64_to_v4i32(<4 x double> %a) #0 {
}
define <4 x i32> @strict_vector_fptoui_v4f64_to_v4i32(<4 x double> %a) #0 {
-; AVX-32-LABEL: strict_vector_fptoui_v4f64_to_v4i32:
-; AVX-32: # %bb.0:
-; AVX-32-NEXT: vmovapd {{.*#+}} ymm1 = [2.147483648E+9,2.147483648E+9,2.147483648E+9,2.147483648E+9]
-; AVX-32-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2
-; AVX-32-NEXT: vextractf128 $1, %ymm2, %xmm3
-; AVX-32-NEXT: vshufps {{.*#+}} xmm3 = xmm2[0,2],xmm3[0,2]
-; AVX-32-NEXT: vxorps %xmm4, %xmm4, %xmm4
-; AVX-32-NEXT: vmovaps {{.*#+}} xmm5 = [2147483648,2147483648,2147483648,2147483648]
-; AVX-32-NEXT: vblendvps %xmm3, %xmm4, %xmm5, %xmm3
-; AVX-32-NEXT: vxorps %xmm4, %xmm4, %xmm4
-; AVX-32-NEXT: vblendvpd %ymm2, %ymm4, %ymm1, %ymm1
-; AVX-32-NEXT: vsubpd %ymm1, %ymm0, %ymm0
-; AVX-32-NEXT: vcvttpd2dq %ymm0, %xmm0
-; AVX-32-NEXT: vxorpd %xmm3, %xmm0, %xmm0
-; AVX-32-NEXT: vzeroupper
-; AVX-32-NEXT: retl
-;
-; AVX-64-LABEL: strict_vector_fptoui_v4f64_to_v4i32:
-; AVX-64: # %bb.0:
-; AVX-64-NEXT: vmovapd {{.*#+}} ymm1 = [2.147483648E+9,2.147483648E+9,2.147483648E+9,2.147483648E+9]
-; AVX-64-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2
-; AVX-64-NEXT: vextractf128 $1, %ymm2, %xmm3
-; AVX-64-NEXT: vshufps {{.*#+}} xmm3 = xmm2[0,2],xmm3[0,2]
-; AVX-64-NEXT: vxorps %xmm4, %xmm4, %xmm4
-; AVX-64-NEXT: vmovaps {{.*#+}} xmm5 = [2147483648,2147483648,2147483648,2147483648]
-; AVX-64-NEXT: vblendvps %xmm3, %xmm4, %xmm5, %xmm3
-; AVX-64-NEXT: vxorps %xmm4, %xmm4, %xmm4
-; AVX-64-NEXT: vblendvpd %ymm2, %ymm4, %ymm1, %ymm1
-; AVX-64-NEXT: vsubpd %ymm1, %ymm0, %ymm0
-; AVX-64-NEXT: vcvttpd2dq %ymm0, %xmm0
-; AVX-64-NEXT: vxorpd %xmm3, %xmm0, %xmm0
-; AVX-64-NEXT: vzeroupper
-; AVX-64-NEXT: retq
+; AVX-LABEL: strict_vector_fptoui_v4f64_to_v4i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vmovapd {{.*#+}} ymm1 = [2.147483648E+9,2.147483648E+9,2.147483648E+9,2.147483648E+9]
+; AVX-NEXT: vcmpltpd %ymm1, %ymm0, %ymm2
+; AVX-NEXT: vextractf128 $1, %ymm2, %xmm3
+; AVX-NEXT: vshufps {{.*#+}} xmm3 = xmm2[0,2],xmm3[0,2]
+; AVX-NEXT: vxorps %xmm4, %xmm4, %xmm4
+; AVX-NEXT: vmovaps {{.*#+}} xmm5 = [2147483648,2147483648,2147483648,2147483648]
+; AVX-NEXT: vblendvps %xmm3, %xmm4, %xmm5, %xmm3
+; AVX-NEXT: vxorps %xmm4, %xmm4, %xmm4
+; AVX-NEXT: vblendvpd %ymm2, %ymm4, %ymm1, %ymm1
+; AVX-NEXT: vsubpd %ymm1, %ymm0, %ymm0
+; AVX-NEXT: vcvttpd2dq %ymm0, %xmm0
+; AVX-NEXT: vxorpd %xmm3, %xmm0, %xmm0
+; AVX-NEXT: vzeroupper
+; AVX-NEXT: ret{{[l|q]}}
;
; AVX512F-LABEL: strict_vector_fptoui_v4f64_to_v4i32:
; AVX512F: # %bb.0:
@@ -1288,17 +1271,11 @@ define <4 x i8> @strict_vector_fptoui_v4f64_to_v4i8(<4 x double> %a) #0 {
}
define <4 x i1> @strict_vector_fptosi_v4f64_to_v4i1(<4 x double> %a) #0 {
-; AVX-32-LABEL: strict_vector_fptosi_v4f64_to_v4i1:
-; AVX-32: # %bb.0:
-; AVX-32-NEXT: vcvttpd2dq %ymm0, %xmm0
-; AVX-32-NEXT: vzeroupper
-; AVX-32-NEXT: retl
-;
-; AVX-64-LABEL: strict_vector_fptosi_v4f64_to_v4i1:
-; AVX-64: # %bb.0:
-; AVX-64-NEXT: vcvttpd2dq %ymm0, %xmm0
-; AVX-64-NEXT: vzeroupper
-; AVX-64-NEXT: retq
+; AVX-LABEL: strict_vector_fptosi_v4f64_to_v4i1:
+; AVX: # %bb.0:
+; AVX-NEXT: vcvttpd2dq %ymm0, %xmm0
+; AVX-NEXT: vzeroupper
+; AVX-NEXT: ret{{[l|q]}}
;
; AVX512F-LABEL: strict_vector_fptosi_v4f64_to_v4i1:
; AVX512F: # %bb.0:
@@ -1340,17 +1317,11 @@ define <4 x i1> @strict_vector_fptosi_v4f64_to_v4i1(<4 x double> %a) #0 {
}
define <4 x i1> @strict_vector_fptoui_v4f64_to_v4i1(<4 x double> %a) #0 {
-; AVX-32-LABEL: strict_vector_fptoui_v4f64_to_v4i1:
-; AVX-32: # %bb.0:
-; AVX-32-NEXT: vcvttpd2dq %ymm0, %xmm0
-; AVX-32-NEXT: vzeroupper
-; AVX-32-NEXT: retl
-;
-; AVX-64-LABEL: strict_vector_fptoui_v4f64_to_v4i1:
-; AVX-64: # %bb.0:
-; AVX-64-NEXT: vcvttpd2dq %ymm0, %xmm0
-; AVX-64-NEXT: vzeroupper
-; AVX-64-NEXT: retq
+; AVX-LABEL: strict_vector_fptoui_v4f64_to_v4i1:
+; AVX: # %bb.0:
+; AVX-NEXT: vcvttpd2dq %ymm0, %xmm0
+; AVX-NEXT: vzeroupper
+; AVX-NEXT: ret{{[l|q]}}
;
; AVX512F-LABEL: strict_vector_fptoui_v4f64_to_v4i1:
; AVX512F: # %bb.0:
@@ -1406,31 +1377,18 @@ define <8 x i32> @strict_vector_fptosi_v8f32_to_v8i32(<8 x float> %a) #0 {
}
define <8 x i32> @strict_vector_fptoui_v8f32_to_v8i32(<8 x float> %a) #0 {
-; AVX-32-LABEL: strict_vector_fptoui_v8f32_to_v8i32:
-; AVX-32: # %bb.0:
-; AVX-32-NEXT: vmovaps {{.*#+}} ymm1 = [2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9]
-; AVX-32-NEXT: vcmpltps %ymm1, %ymm0, %ymm2
-; AVX-32-NEXT: vxorps %xmm3, %xmm3, %xmm3
-; AVX-32-NEXT: vmovaps {{.*#+}} ymm4 = [2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648]
-; AVX-32-NEXT: vblendvps %ymm2, %ymm3, %ymm4, %ymm4
-; AVX-32-NEXT: vblendvps %ymm2, %ymm3, %ymm1, %ymm1
-; AVX-32-NEXT: vsubps %ymm1, %ymm0, %ymm0
-; AVX-32-NEXT: vcvttps2dq %ymm0, %ymm0
-; AVX-32-NEXT: vxorps %ymm4, %ymm0, %ymm0
-; AVX-32-NEXT: retl
-;
-; AVX-64-LABEL: strict_vector_fptoui_v8f32_to_v8i32:
-; AVX-64: # %bb.0:
-; AVX-64-NEXT: vmovaps {{.*#+}} ymm1 = [2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9]
-; AVX-64-NEXT: vcmpltps %ymm1, %ymm0, %ymm2
-; AVX-64-NEXT: vxorps %xmm3, %xmm3, %xmm3
-; AVX-64-NEXT: vmovaps {{.*#+}} ymm4 = [2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648]
-; AVX-64-NEXT: vblendvps %ymm2, %ymm3, %ymm4, %ymm4
-; AVX-64-NEXT: vblendvps %ymm2, %ymm3, %ymm1, %ymm1
-; AVX-64-NEXT: vsubps %ymm1, %ymm0, %ymm0
-; AVX-64-NEXT: vcvttps2dq %ymm0, %ymm0
-; AVX-64-NEXT: vxorps %ymm4, %ymm0, %ymm0
-; AVX-64-NEXT: retq
+; AVX-LABEL: strict_vector_fptoui_v8f32_to_v8i32:
+; AVX: # %bb.0:
+; AVX-NEXT: vmovaps {{.*#+}} ymm1 = [2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9]
+; AVX-NEXT: vcmpltps %ymm1, %ymm0, %ymm2
+; AVX-NEXT: vxorps %xmm3, %xmm3, %xmm3
+; AVX-NEXT: vmovaps {{.*#+}} ymm4 = [2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648]
+; AVX-NEXT: vblendvps %ymm2, %ymm3, %ymm4, %ymm4
+; AVX-NEXT: vblendvps %ymm2, %ymm3, %ymm1, %ymm1
+; AVX-NEXT: vsubps %ymm1, %ymm0, %ymm0
+; AVX-NEXT: vcvttps2dq %ymm0, %ymm0
+; AVX-NEXT: vxorps %ymm4, %ymm0, %ymm0
+; AVX-NEXT: ret{{[l|q]}}
;
; AVX512F-LABEL: strict_vector_fptoui_v8f32_to_v8i32:
; AVX512F: # %bb.0:
@@ -1461,21 +1419,13 @@ define <8 x i32> @strict_vector_fptoui_v8f32_to_v8i32(<8 x float> %a) #0 {
}
define <8 x i16> @strict_vector_fptosi_v8f32_to_v8i16(<8 x float> %a) #0 {
-; AVX-32-LABEL: strict_vector_fptosi_v8f32_to_v8i16:
-; AVX-32: # %bb.0:
-; AVX-32-NEXT: vcvttps2dq %ymm0, %ymm0
-; AVX-32-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-32-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
-; AVX-32-NEXT: vzeroupper
-; AVX-32-NEXT: retl
-;
-; AVX-64-LABEL: strict_vector_fptosi_v8f32_to_v8i16:
-; AVX-64: # %bb.0:
-; AVX-64-NEXT: vcvttps2dq %ymm0, %ymm0
-; AVX-64-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-64-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
-; AVX-64-NEXT: vzeroupper
-; AVX-64-NEXT: retq
+; AVX-LABEL: strict_vector_fptosi_v8f32_to_v8i16:
+; AVX: # %bb.0:
+; AVX-NEXT: vcvttps2dq %ymm0, %ymm0
+; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vzeroupper
+; AVX-NEXT: ret{{[l|q]}}
;
; AVX512F-LABEL: strict_vector_fptosi_v8f32_to_v8i16:
; AVX512F: # %bb.0:
@@ -1512,21 +1462,13 @@ define <8 x i16> @strict_vector_fptosi_v8f32_to_v8i16(<8 x float> %a) #0 {
}
define <8 x i16> @strict_vector_fptoui_v8f32_to_v8i16(<8 x float> %a) #0 {
-; AVX-32-LABEL: strict_vector_fptoui_v8f32_to_v8i16:
-; AVX-32: # %bb.0:
-; AVX-32-NEXT: vcvttps2dq %ymm0, %ymm0
-; AVX-32-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-32-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
-; AVX-32-NEXT: vzeroupper
-; AVX-32-NEXT: retl
-;
-; AVX-64-LABEL: strict_vector_fptoui_v8f32_to_v8i16:
-; AVX-64: # %bb.0:
-; AVX-64-NEXT: vcvttps2dq %ymm0, %ymm0
-; AVX-64-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-64-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
-; AVX-64-NEXT: vzeroupper
-; AVX-64-NEXT: retq
+; AVX-LABEL: strict_vector_fptoui_v8f32_to_v8i16:
+; AVX: # %bb.0:
+; AVX-NEXT: vcvttps2dq %ymm0, %ymm0
+; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vzeroupper
+; AVX-NEXT: ret{{[l|q]}}
;
; AVX512F-LABEL: strict_vector_fptoui_v8f32_to_v8i16:
; AVX512F: # %bb.0:
@@ -1563,23 +1505,14 @@ define <8 x i16> @strict_vector_fptoui_v8f32_to_v8i16(<8 x float> %a) #0 {
}
define <8 x i8> @strict_vector_fptosi_v8f32_to_v8i8(<8 x float> %a) #0 {
-; AVX-32-LABEL: strict_vector_fptosi_v8f32_to_v8i8:
-; AVX-32: # %bb.0:
-; AVX-32-NEXT: vcvttps2dq %ymm0, %ymm0
-; AVX-32-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-32-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
-; AVX-32-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
-; AVX-32-NEXT: vzeroupper
-; AVX-32-NEXT: retl
-;
-; AVX-64-LABEL: strict_vector_fptosi_v8f32_to_v8i8:
-; AVX-64: # %bb.0:
-; AVX-64-NEXT: vcvttps2dq %ymm0, %ymm0
-; AVX-64-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-64-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
-; AVX-64-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
-; AVX-64-NEXT: vzeroupper
-; AVX-64-NEXT: retq
+; AVX-LABEL: strict_vector_fptosi_v8f32_to_v8i8:
+; AVX: # %bb.0:
+; AVX-NEXT: vcvttps2dq %ymm0, %ymm0
+; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vpacksswb %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vzeroupper
+; AVX-NEXT: ret{{[l|q]}}
;
; AVX512F-LABEL: strict_vector_fptosi_v8f32_to_v8i8:
; AVX512F: # %bb.0:
@@ -1614,23 +1547,14 @@ define <8 x i8> @strict_vector_fptosi_v8f32_to_v8i8(<8 x float> %a) #0 {
}
define <8 x i8> @strict_vector_fptoui_v8f32_to_v8i8(<8 x float> %a) #0 {
-; AVX-32-LABEL: strict_vector_fptoui_v8f32_to_v8i8:
-; AVX-32: # %bb.0:
-; AVX-32-NEXT: vcvttps2dq %ymm0, %ymm0
-; AVX-32-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-32-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
-; AVX-32-NEXT: vpackuswb %xmm0, %xmm0, %xmm0
-; AVX-32-NEXT: vzeroupper
-; AVX-32-NEXT: retl
-;
-; AVX-64-LABEL: strict_vector_fptoui_v8f32_to_v8i8:
-; AVX-64: # %bb.0:
-; AVX-64-NEXT: vcvttps2dq %ymm0, %ymm0
-; AVX-64-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-64-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
-; AVX-64-NEXT: vpackuswb %xmm0, %xmm0, %xmm0
-; AVX-64-NEXT: vzeroupper
-; AVX-64-NEXT: retq
+; AVX-LABEL: strict_vector_fptoui_v8f32_to_v8i8:
+; AVX: # %bb.0:
+; AVX-NEXT: vcvttps2dq %ymm0, %ymm0
+; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vpackuswb %xmm0, %xmm0, %xmm0
+; AVX-NEXT: vzeroupper
+; AVX-NEXT: ret{{[l|q]}}
;
; AVX512F-LABEL: strict_vector_fptoui_v8f32_to_v8i8:
; AVX512F: # %bb.0:
@@ -1665,21 +1589,13 @@ define <8 x i8> @strict_vector_fptoui_v8f32_to_v8i8(<8 x float> %a) #0 {
}
define <8 x i1> @strict_vector_fptosi_v8f32_to_v8i1(<8 x float> %a) #0 {
-; AVX-32-LABEL: strict_vector_fptosi_v8f32_to_v8i1:
-; AVX-32: # %bb.0:
-; AVX-32-NEXT: vcvttps2dq %ymm0, %ymm0
-; AVX-32-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-32-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
-; AVX-32-NEXT: vzeroupper
-; AVX-32-NEXT: retl
-;
-; AVX-64-LABEL: strict_vector_fptosi_v8f32_to_v8i1:
-; AVX-64: # %bb.0:
-; AVX-64-NEXT: vcvttps2dq %ymm0, %ymm0
-; AVX-64-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-64-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
-; AVX-64-NEXT: vzeroupper
-; AVX-64-NEXT: retq
+; AVX-LABEL: strict_vector_fptosi_v8f32_to_v8i1:
+; AVX: # %bb.0:
+; AVX-NEXT: vcvttps2dq %ymm0, %ymm0
+; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vzeroupper
+; AVX-NEXT: ret{{[l|q]}}
;
; AVX512F-LABEL: strict_vector_fptosi_v8f32_to_v8i1:
; AVX512F: # %bb.0:
@@ -1725,21 +1641,13 @@ define <8 x i1> @strict_vector_fptosi_v8f32_to_v8i1(<8 x float> %a) #0 {
}
define <8 x i1> @strict_vector_fptoui_v8f32_to_v8i1(<8 x float> %a) #0 {
-; AVX-32-LABEL: strict_vector_fptoui_v8f32_to_v8i1:
-; AVX-32: # %bb.0:
-; AVX-32-NEXT: vcvttps2dq %ymm0, %ymm0
-; AVX-32-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-32-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
-; AVX-32-NEXT: vzeroupper
-; AVX-32-NEXT: retl
-;
-; AVX-64-LABEL: strict_vector_fptoui_v8f32_to_v8i1:
-; AVX-64: # %bb.0:
-; AVX-64-NEXT: vcvttps2dq %ymm0, %ymm0
-; AVX-64-NEXT: vextractf128 $1, %ymm0, %xmm1
-; AVX-64-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
-; AVX-64-NEXT: vzeroupper
-; AVX-64-NEXT: retq
+; AVX-LABEL: strict_vector_fptoui_v8f32_to_v8i1:
+; AVX: # %bb.0:
+; AVX-NEXT: vcvttps2dq %ymm0, %ymm0
+; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
+; AVX-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
+; AVX-NEXT: vzeroupper
+; AVX-NEXT: ret{{[l|q]}}
;
; AVX512F-LABEL: strict_vector_fptoui_v8f32_to_v8i1:
; AVX512F: # %bb.0:
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