[PATCH] D76720: [Transforms][SROA] Disable pass for scalable vectors

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes added a comment.

In D76720#1939896 <https://reviews.llvm.org/D76720#1939896>, @efriedma wrote:

> We want SROA to at least run mem2reg on scalable vectors, since we don't run mem2reg separately.  This is important for C code using SVE intrinsics.


I've tested this on Sander's Clang patch (D76238 <https://reviews.llvm.org/D76238>) adding contiguous loads/stores upstream and mem2reg runs:

  $ /home/culrho01/llvm-project/build/bin/clang -cc1 -internal-isystem /home/culrho01/llvm-project/build/lib/clang/11.0.0/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -emit-llvm -o - /home/culrho01/llvm-project/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1.c -D__ARM_FEATURE_SVE -mllvm -print-before-all -mllvm -print-after-all
  
  *** IR Dump Before Promote Memory to Register ***
  ; Function Attrs: nounwind
  define <vscale x 16 x i8> @test_svld1_s8(<vscale x 16 x i1> %pg, i8* %base) local_unnamed_addr #0 {
  entry:
    %pg.addr = alloca <vscale x 16 x i1>, align 2
    store <vscale x 16 x i1> %pg, <vscale x 16 x i1>* %pg.addr, align 2, !tbaa !2
    %0 = bitcast i8* %base to <vscale x 16 x i8>*
    %1 = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0nxv16i8(<vscale x 16 x i8>* %0, i32 1, <vscale x 16 x i1> %pg, <vscale x 16 x i8> zeroinitializer)
    ret <vscale x 16 x i8> %1
  }
  *** IR Dump After Promote Memory to Register ***
  ; Function Attrs: nounwind
  define <vscale x 16 x i8> @test_svld1_s8(<vscale x 16 x i1> %pg, i8* %base) local_unnamed_addr #0 {
  entry:
    %0 = bitcast i8* %base to <vscale x 16 x i8>*
    %1 = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0nxv16i8(<vscale x 16 x i8>* %0, i32 1, <vscale x 16 x i1> %pg, <vscale x 16 x i8> zeroinitializer)
    ret <vscale x 16 x i8> %1
  }``


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D76720/new/

https://reviews.llvm.org/D76720