[PATCH] D76720: [Transforms][SROA] Disable pass for scalable vectors

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes added a comment.

In D76720#1939896 <https://reviews.llvm.org/D76720#1939896>, @efriedma wrote:

> We want SROA to at least run mem2reg on scalable vectors, since we don't run mem2reg separately.  This is important for C code using SVE intrinsics.


mem2reg isn't run as a separate pass? We have a clang ACLE test for brka intrinsic downstream that was hitting a lot of `"Request for a fixed size on a scalable object"` asserts in SROA, with this patch applied it gets optimised by mem2reg:

  ./build/bin/clang -cc1 -internal-isystem ./build/lib/clang/9.0.1/include -nostdsysteminc -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o -  tools/clang/test/CodeGen/AArch64/acle/acle_sve_brka.c -mllvm -print-before-pass=mem2reg -mllvm -print-after-pass=mem2reg
  *** IR Dump Before Promote Memory to Register ***
  ; Function Attrs: nounwind
  define <n x 16 x i1> @test_svbrka_b_z(<n x 16 x i1> %pg, <n x 16 x i1> %op) local_unnamed_addr #0 {
  entry:
    %pg.addr = alloca <n x 16 x i1>, align 1
    %op.addr = alloca <n x 16 x i1>, align 1
    store <n x 16 x i1> %pg, <n x 16 x i1>* %pg.addr, align 1, !tbaa !2
    store <n x 16 x i1> %op, <n x 16 x i1>* %op.addr, align 1, !tbaa !2
    %0 = load <n x 16 x i1>, <n x 16 x i1>* %pg.addr, align 1, !tbaa !2
    %1 = call <n x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<n x 16 x i1> %0, <n x 16 x i1> %op)
    ret <n x 16 x i1> %1
  }
  *** IR Dump After Promote Memory to Register ***
  ; Function Attrs: nounwind
  define <n x 16 x i1> @test_svbrka_b_z(<n x 16 x i1> %pg, <n x 16 x i1> %op) local_unnamed_addr #0 {
  entry:
    %0 = call <n x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<n x 16 x i1> %pg, <n x 16 x i1> %op)
    ret <n x 16 x i1> %0
  }

I ran our downstream unit tests with SROA disabled and there's no asm differences.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76720/new/

https://reviews.llvm.org/D76720