[PATCH] D76716: [ARM][MVE] Tail predicate VMAXV(unsigned) and VMAXAV

[Sam Parker via Phabricator via llvm-commits]

samparker added a comment.

> The unit test failure looks genuine, does that needs fixing?

Ah, I haven't updated the unit test in D76708 <https://reviews.llvm.org/D76708>.

For min/max, we can't support an implicit vmin because the results may not be the same after the conversion. So, say we only have three 32-bit elements left to process (and the fourth element is the LHS 0x00):

| opcode    | input      | original result | tail predicated result |
| VMAXV.u32 | 0x00010203 | 0x03            | 0x03                   |
| VMINV.u32 | 0x00010203 | 0x00            | 0x01                   |
|

The tail predicated instruction will ignore the predicated lanes/bytes, whereas the original doesn't.
We're also only supporting unsigned values because we know that the 'FalseLaneZeros' can't interfere with the result, because the zero will only be the answer if the rest of the elements are also zero. This is not true for signed values though, where the false zero may be the largest value.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D76716/new/

https://reviews.llvm.org/D76716