[llvm] 9bbddfb - [mips] Implement sne pseudo instruction
Simon Atanasyan via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 22 13:36:43 PDT 2020
Author: Simon Atanasyan
Date: 2020-03-22T23:34:31+03:00
New Revision: 9bbddfbeaabd44f90ab56bae35b6092b0a9818fa
URL: https://github.com/llvm/llvm-project/commit/9bbddfbeaabd44f90ab56bae35b6092b0a9818fa
DIFF: https://github.com/llvm/llvm-project/commit/9bbddfbeaabd44f90ab56bae35b6092b0a9818fa.diff
LOG: [mips] Implement sne pseudo instruction
The `sne Dst, Src1, Src2/Imm` pseudo instruction sets register `Dst` to
1 if register `Src1` is not equal to `Src2/Imm` and to 0 otherwise.
Added:
llvm/test/MC/Mips/macro-sne.s
Modified:
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/lib/Target/Mips/MipsInstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 4e7410c27f06..79de8d746d86 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -340,6 +340,12 @@ class MipsAsmParser : public MCTargetAsmParser {
bool expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
+ bool expandSne(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+ const MCSubtargetInfo *STI);
+
+ bool expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+ const MCSubtargetInfo *STI);
+
bool expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
@@ -2605,6 +2611,10 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
return expandSeq(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::SEQIMacro:
return expandSeqI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
+ case Mips::SNEMacro:
+ return expandSne(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
+ case Mips::SNEIMacro:
+ return expandSneI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::MFTC0: case Mips::MTTC0:
case Mips::MFTGPR: case Mips::MTTGPR:
case Mips::MFTLO: case Mips::MTTLO:
@@ -5424,6 +5434,88 @@ bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
return false;
}
+bool MipsAsmParser::expandSne(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+ const MCSubtargetInfo *STI) {
+
+ MipsTargetStreamer &TOut = getTargetStreamer();
+
+ assert(Inst.getNumOperands() == 3 && "Invalid operand count");
+ assert(Inst.getOperand(0).isReg() &&
+ Inst.getOperand(1).isReg() &&
+ Inst.getOperand(2).isReg() && "Invalid instruction operand.");
+
+ unsigned DstReg = Inst.getOperand(0).getReg();
+ unsigned SrcReg = Inst.getOperand(1).getReg();
+ unsigned OpReg = Inst.getOperand(2).getReg();
+
+ warnIfNoMacro(IDLoc);
+
+ if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) {
+ TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI);
+ TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI);
+ return false;
+ }
+
+ unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg;
+ TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, Reg, IDLoc, STI);
+ return false;
+}
+
+bool MipsAsmParser::expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+ const MCSubtargetInfo *STI) {
+ MipsTargetStreamer &TOut = getTargetStreamer();
+
+ assert(Inst.getNumOperands() == 3 && "Invalid operand count");
+ assert(Inst.getOperand(0).isReg() &&
+ Inst.getOperand(1).isReg() &&
+ Inst.getOperand(2).isImm() && "Invalid instruction operand.");
+
+ unsigned DstReg = Inst.getOperand(0).getReg();
+ unsigned SrcReg = Inst.getOperand(1).getReg();
+ int64_t ImmValue = Inst.getOperand(2).getImm();
+
+ warnIfNoMacro(IDLoc);
+
+ if (ImmValue == 0) {
+ TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, SrcReg, IDLoc, STI);
+ return false;
+ }
+
+ if (SrcReg == Mips::ZERO) {
+ Warning(IDLoc, "comparison is always true");
+ if (loadImmediate(1, DstReg, Mips::NoRegister, true, false, IDLoc, Out,
+ STI))
+ return true;
+ return false;
+ }
+
+ unsigned Opc;
+ if (ImmValue > -0x8000 && ImmValue < 0) {
+ ImmValue = -ImmValue;
+ Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu;
+ } else {
+ Opc = Mips::XORi;
+ }
+
+ if (isUInt<16>(ImmValue)) {
+ TOut.emitRRI(Opc, DstReg, SrcReg, ImmValue, IDLoc, STI);
+ TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI);
+ return false;
+ }
+
+ unsigned ATReg = getATReg(IDLoc);
+ if (!ATReg)
+ return true;
+
+ if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, isInt<32>(ImmValue),
+ false, IDLoc, Out, STI))
+ return true;
+
+ TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI);
+ TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI);
+ return false;
+}
+
// Map the DSP accumulator and control register to the corresponding gpr
// operand. Unlike the other alias, the m(f|t)t(lo|hi|acx) instructions
// do not map the DSP registers contigously to gpr registers.
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index 4e27324aa639..ad964df2ea42 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -2589,6 +2589,22 @@ def : MipsInstAlias<"seq $rd, $imm",
(SEQIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, simm32:$imm), 0>,
NOT_ASE_CNMIPS;
+def SNEMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+ (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+ "sne $rd, $rs, $rt">, NOT_ASE_CNMIPS;
+
+def : MipsInstAlias<"sne $rd, $rs",
+ (SNEMacro GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>,
+ NOT_ASE_CNMIPS;
+
+def SNEIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+ (ins GPR32Opnd:$rs, simm32_relaxed:$imm),
+ "sne $rd, $rs, $imm">, NOT_ASE_CNMIPS;
+
+def : MipsInstAlias<"sne $rd, $imm",
+ (SNEIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, simm32:$imm), 0>,
+ NOT_ASE_CNMIPS;
+
def MULImmMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs,
simm32_relaxed:$imm),
"mul\t$rd, $rs, $imm">,
diff --git a/llvm/test/MC/Mips/macro-sne.s b/llvm/test/MC/Mips/macro-sne.s
new file mode 100644
index 000000000000..497e1d604c41
--- /dev/null
+++ b/llvm/test/MC/Mips/macro-sne.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips1 < %s \
+# RUN: | FileCheck --check-prefixes=ALL,MIPS32 %s
+# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips64 < %s \
+# RUN: | FileCheck --check-prefixes=ALL,MIPS64 %s
+
+sne $4, $5, $6
+# ALL: xor $4, $5, $6 # encoding: [0x00,0xa6,0x20,0x26]
+# ALL: sltu $4, $zero, $4 # encoding: [0x00,0x04,0x20,0x2b]
+sne $4, $zero, $6
+# ALL: sltu $4, $zero, $6 # encoding: [0x00,0x06,0x20,0x2b]
+sne $4, $5, $zero
+# ALL: sltu $4, $zero, $5 # encoding: [0x00,0x05,0x20,0x2b]
+sne $4, $5, 0
+# ALL: sltu $4, $zero, $5 # encoding: [0x00,0x05,0x20,0x2b]
+sne $4, $zero, 1
+# ALL: addiu $4, $zero, 1 # encoding: [0x24,0x04,0x00,0x01]
+sne $4, $5, -1
+# MIPS32: addiu $4, $5, 1 # encoding: [0x24,0xa4,0x00,0x01]
+# MIPS64: daddiu $4, $5, 1 # encoding: [0x64,0xa4,0x00,0x01]
+# ALL: sltu $4, $zero, $4 # encoding: [0x00,0x04,0x20,0x2b]
+sne $4, $5, 1
+# ALL: xori $4, $5, 1 # encoding: [0x38,0xa4,0x00,0x01]
+# ALL: sltu $4, $zero, $4 # encoding: [0x00,0x04,0x20,0x2b]
+sne $4, $5, 0x10000
+# ALL: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01]
+# ALL: xor $4, $5, $1 # encoding: [0x00,0xa1,0x20,0x26]
+# ALL: sltu $4, $zero, $4 # encoding: [0x00,0x04,0x20,0x2b]
More information about the llvm-commits
mailing list