[llvm] dca9e40 - [mips] Implement sle/sleu pseudo instructions
Simon Atanasyan via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 22 13:36:41 PDT 2020
Author: Simon Atanasyan
Date: 2020-03-22T23:34:31+03:00
New Revision: dca9e40c0cf8fdf154c4da50c45515a910583318
URL: https://github.com/llvm/llvm-project/commit/dca9e40c0cf8fdf154c4da50c45515a910583318
DIFF: https://github.com/llvm/llvm-project/commit/dca9e40c0cf8fdf154c4da50c45515a910583318.diff
LOG: [mips] Implement sle/sleu pseudo instructions
The `sle/sleu Dst, Src1, Src2/Imm` pseudo instructions set register
`Dst` to 1 if register `Src1` is less than or equal `Src2/Imm` and
to 0 otherwise.
Added:
llvm/test/MC/Mips/macro-sle.s
llvm/test/MC/Mips/macro-sle64.s
Modified:
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
llvm/lib/Target/Mips/Mips64InstrInfo.td
llvm/lib/Target/Mips/MipsInstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index df1d2d083232..4e7410c27f06 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -298,6 +298,12 @@ class MipsAsmParser : public MCTargetAsmParser {
bool expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI);
+ bool expandSle(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+ const MCSubtargetInfo *STI);
+
+ bool expandSleImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+ const MCSubtargetInfo *STI);
+
bool expandRotation(MCInst &Inst, SMLoc IDLoc,
MCStreamer &Out, const MCSubtargetInfo *STI);
bool expandRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
@@ -2515,6 +2521,14 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
case Mips::SGTImm64:
case Mips::SGTUImm64:
return expandSgtImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
+ case Mips::SLE:
+ case Mips::SLEU:
+ return expandSle(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
+ case Mips::SLEImm:
+ case Mips::SLEUImm:
+ case Mips::SLEImm64:
+ case Mips::SLEUImm64:
+ return expandSleImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::SLTImm64:
if (isInt<16>(Inst.getOperand(2).getImm())) {
Inst.setOpcode(Mips::SLTi64);
@@ -4639,6 +4653,88 @@ bool MipsAsmParser::expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
return false;
}
+bool MipsAsmParser::expandSle(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+ const MCSubtargetInfo *STI) {
+ MipsTargetStreamer &TOut = getTargetStreamer();
+
+ assert(Inst.getNumOperands() == 3 && "Invalid operand count");
+ assert(Inst.getOperand(0).isReg() &&
+ Inst.getOperand(1).isReg() &&
+ Inst.getOperand(2).isReg() && "Invalid instruction operand.");
+
+ unsigned DstReg = Inst.getOperand(0).getReg();
+ unsigned SrcReg = Inst.getOperand(1).getReg();
+ unsigned OpReg = Inst.getOperand(2).getReg();
+ unsigned OpCode;
+
+ warnIfNoMacro(IDLoc);
+
+ switch (Inst.getOpcode()) {
+ case Mips::SLE:
+ OpCode = Mips::SLT;
+ break;
+ case Mips::SLEU:
+ OpCode = Mips::SLTu;
+ break;
+ default:
+ llvm_unreachable("unexpected 'sge' opcode");
+ }
+
+ // $SrcReg <= $OpReg is equal to (not ($OpReg < $SrcReg))
+ TOut.emitRRR(OpCode, DstReg, OpReg, SrcReg, IDLoc, STI);
+ TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
+
+ return false;
+}
+
+bool MipsAsmParser::expandSleImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+ const MCSubtargetInfo *STI) {
+ MipsTargetStreamer &TOut = getTargetStreamer();
+
+ assert(Inst.getNumOperands() == 3 && "Invalid operand count");
+ assert(Inst.getOperand(0).isReg() &&
+ Inst.getOperand(1).isReg() &&
+ Inst.getOperand(2).isImm() && "Invalid instruction operand.");
+
+ unsigned DstReg = Inst.getOperand(0).getReg();
+ unsigned SrcReg = Inst.getOperand(1).getReg();
+ int64_t ImmValue = Inst.getOperand(2).getImm();
+ unsigned OpRegCode;
+
+ warnIfNoMacro(IDLoc);
+
+ switch (Inst.getOpcode()) {
+ case Mips::SLEImm:
+ case Mips::SLEImm64:
+ OpRegCode = Mips::SLT;
+ break;
+ case Mips::SLEUImm:
+ case Mips::SLEUImm64:
+ OpRegCode = Mips::SLTu;
+ break;
+ default:
+ llvm_unreachable("unexpected 'sge' opcode with immediate");
+ }
+
+ // $SrcReg <= Imm is equal to (not (Imm < $SrcReg))
+ unsigned ImmReg = DstReg;
+ if (DstReg == SrcReg) {
+ unsigned ATReg = getATReg(Inst.getLoc());
+ if (!ATReg)
+ return true;
+ ImmReg = ATReg;
+ }
+
+ if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
+ false, IDLoc, Out, STI))
+ return true;
+
+ TOut.emitRRR(OpRegCode, DstReg, ImmReg, SrcReg, IDLoc, STI);
+ TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
+
+ return false;
+}
+
bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc,
MCStreamer &Out,
const MCSubtargetInfo *STI) {
diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td
index 306289d56e4b..bd62a56d3008 100644
--- a/llvm/lib/Target/Mips/Mips64InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td
@@ -1248,5 +1248,19 @@ def : MipsInstAlias<"sgtu $rs, $imm", (SGTUImm64 GPR64Opnd:$rs,
GPR64Opnd:$rs,
imm64:$imm), 0>, GPR_64;
+def SLEImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
+ (ins GPR64Opnd:$rs, imm64:$imm),
+ "sle\t$rd, $rs, $imm">, GPR_64;
+def : MipsInstAlias<"sle $rs, $imm", (SLEImm64 GPR64Opnd:$rs,
+ GPR64Opnd:$rs,
+ imm64:$imm), 0>, GPR_64;
+
+def SLEUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
+ (ins GPR64Opnd:$rs, imm64:$imm),
+ "sleu\t$rd, $rs, $imm">, GPR_64;
+def : MipsInstAlias<"sleu $rs, $imm", (SLEUImm64 GPR64Opnd:$rs,
+ GPR64Opnd:$rs,
+ imm64:$imm), 0>, GPR_64;
+
def : MipsInstAlias<"rdhwr $rt, $rs",
(RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, GPR_64;
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index eabfdcf912d6..4e27324aa639 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -2736,6 +2736,34 @@ let AdditionalPredicates = [NotInMicroMips] in {
uimm32_coerced:$imm), 0>,
GPR_32;
+ def SLE : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+ (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+ "sle\t$rd, $rs, $rt">, ISA_MIPS1;
+ def : MipsInstAlias<"sle $rs, $rt",
+ (SLE GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,
+ ISA_MIPS1;
+ def SLEImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+ (ins GPR32Opnd:$rs, simm32:$imm),
+ "sle\t$rd, $rs, $imm">, GPR_32;
+ def : MipsInstAlias<"sle $rs, $imm", (SLEImm GPR32Opnd:$rs,
+ GPR32Opnd:$rs,
+ simm32:$imm), 0>,
+ GPR_32;
+
+ def SLEU : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+ (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
+ "sleu\t$rd, $rs, $rt">, ISA_MIPS1;
+ def : MipsInstAlias<"sleu $rs, $rt",
+ (SLEU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,
+ ISA_MIPS1;
+ def SLEUImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
+ (ins GPR32Opnd:$rs, uimm32_coerced:$imm),
+ "sleu\t$rd, $rs, $imm">, GPR_32;
+ def : MipsInstAlias<"sleu $rs, $imm", (SLEUImm GPR32Opnd:$rs,
+ GPR32Opnd:$rs,
+ uimm32_coerced:$imm), 0>,
+ GPR_32;
+
def : MipsInstAlias<
"not $rt, $rs",
(NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>, ISA_MIPS1;
diff --git a/llvm/test/MC/Mips/macro-sle.s b/llvm/test/MC/Mips/macro-sle.s
new file mode 100644
index 000000000000..6d93ce5b820b
--- /dev/null
+++ b/llvm/test/MC/Mips/macro-sle.s
@@ -0,0 +1,31 @@
+# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips1 < %s | FileCheck %s
+# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips64 < %s | FileCheck %s
+
+sle $4, $5
+# CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
+# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sle $4, $5, $6
+# CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
+# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sle $4, $5, 16
+# CHECK: addiu $4, $zero, 16 # encoding: [0x24,0x04,0x00,0x10]
+# CHECK: slt $4, $4, $5 # encoding: [0x00,0x85,0x20,0x2a]
+# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sleu $4, $5
+# CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
+# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sleu $4, $5, $6
+# CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
+# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sleu $4, $5, 16
+# CHECK: addiu $4, $zero, 16 # encoding: [0x24,0x04,0x00,0x10]
+# CHECK: sltu $4, $4, $5 # encoding: [0x00,0x85,0x20,0x2b]
+# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sle $4, 16
+# CHECK: addiu $1, $zero, 16 # encoding: [0x24,0x01,0x00,0x10]
+# CHECK: slt $4, $1, $4 # encoding: [0x00,0x24,0x20,0x2a]
+# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sleu $4, 16
+# CHECK: addiu $1, $zero, 16 # encoding: [0x24,0x01,0x00,0x10]
+# CHECK: sltu $4, $1, $4 # encoding: [0x00,0x24,0x20,0x2b]
+# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
diff --git a/llvm/test/MC/Mips/macro-sle64.s b/llvm/test/MC/Mips/macro-sle64.s
new file mode 100644
index 000000000000..62ad7c81f9dd
--- /dev/null
+++ b/llvm/test/MC/Mips/macro-sle64.s
@@ -0,0 +1,29 @@
+# RUN: not llvm-mc -arch=mips -mcpu=mips1 < %s 2>&1 \
+# RUN: | FileCheck --check-prefix=MIPS32 %s
+# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips64 < %s \
+# RUN: | FileCheck --check-prefix=MIPS64 %s
+
+sle $4, $5, 0x100000000
+# MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+# MIPS64: ori $4, $zero, 32768 # encoding: [0x34,0x04,0x80,0x00]
+# MIPS64: dsll $4, $4, 17 # encoding: [0x00,0x04,0x24,0x78]
+# MIPS64: slt $4, $4, $5 # encoding: [0x00,0x85,0x20,0x2a]
+# MIPS64: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sleu $4, $5, 0x100000000
+# MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+# MIPS64: ori $4, $zero, 32768 # encoding: [0x34,0x04,0x80,0x00]
+# MIPS64: dsll $4, $4, 17 # encoding: [0x00,0x04,0x24,0x78]
+# MIPS64: sltu $4, $4, $5 # encoding: [0x00,0x85,0x20,0x2b]
+# MIPS64: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sle $4, 0x100000000
+# MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+# MIPS64: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00]
+# MIPS64: dsll $1, $1, 17 # encoding: [0x00,0x01,0x0c,0x78]
+# MIPS64: slt $4, $1, $4 # encoding: [0x00,0x24,0x20,0x2a]
+# MIPS64: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
+sleu $4, 0x100000000
+# MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+# MIPS64: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00]
+# MIPS64: dsll $1, $1, 17 # encoding: [0x00,0x01,0x0c,0x78]
+# MIPS64: sltu $4, $1, $4 # encoding: [0x00,0x24,0x20,0x2b]
+# MIPS64: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
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