[PATCH] D75751: [AArch64][SVE] Implement structured load intrinsics

[Francesco Petrogalli via Phabricator via llvm-commits]

fpetrogalli added inline comments.


================
Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:806
+  class AdvSIMD_ManyVec_PredLoad_Intrinsic
+    : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, llvm_anyptr_ty],
+                [IntrReadMem, IntrArgMemOnly]>;
----------------
Question: you have three overloaded operands here. How comes that you need to specify only one of them in the intrinsic name?

If I look at one of your tests:

```
  %res = call <vscale x 32 x i8> @llvm.aarch64.sve.ld2.nxv32i8(<vscale x 16 x i1> %pred,
                                                               <vscale x 16 x i8>* %addr)
```

By the definition you have specified here, I was expecting to see the following intrinsic: `@llvm.aarch64.sve.ld2.nxv32i8.nxv16i8.p0nxv16i8`. Am I missing something?


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