[PATCH] D75751: [AArch64][SVE] Implement structured load intrinsics

[Francesco Petrogalli via Phabricator via llvm-commits]

fpetrogalli added a comment.

Hi @c-rhodes ,

thank you for working on this. I am basing the addressing mode optimization for `ldN` on this patch, I just wanted to point out a couple of minor remarks!

Grazie,

Francesco

[Nit] Should use `vscale` instead of `n` in the commit message:

  LD2 : <n x 8 x i32>
  LD3 : <n x 12 x i32>
  LD4 : <n x 16 x i32>



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:1394
+                                               const unsigned Opc,
+                                               unsigned SubRegIdx) {
+  SDLoc dl(N);
----------------
`SubRegIdx` is always set to `AArch64::zsub0`. Can we remove it from the parameter list of the method and use `AArch64::zsub0` directly inside the function?


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:9671
+  EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
+                                 VT.getVectorElementCount() / N);
+  assert(isTypeLegal(SplitVT));
----------------
[Nit] Might be worth asserting that `VT.getVectorElementCount() % N == 0`.


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