[PATCH] D75857: [AMDGPU] Fix using physical registers in vector instructions

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Mar 11 09:37:12 PDT 2020

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arsenm added a comment.

I still think theses should not be seeing physical register operands, and it would be better to fix this by avoiding that situation


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75857/new/

https://reviews.llvm.org/D75857

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