[PATCH] D75931: [PowerPC][Future] Add initial support for PC Relative addressing to get jump table base address

[Victor Huang via Phabricator via llvm-commits]

NeHuang created this revision.
NeHuang added reviewers: nemanjai, lei, stefanp, power-llvm-team.
NeHuang added a project: LLVM.
Herald added subscribers: llvm-commits, shchenz, kbarton, hiraditya.

Add initial support for PCRelative addressing to get jump table base address instead of using TOC.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D75931

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/jump-table.ll


Index: llvm/test/CodeGen/PowerPC/jump-table.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/jump-table.ll
@@ -0,0 +1,43 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=future -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN:   --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=future -ppc-use-absolute-jumptables \
+; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN:   --check-prefix=CHECK
+
+define dso_local signext i32 @jumptable(i32 signext %param) {
+; CHECK-LABEL: jumptable:
+; CHECK:       # %bb.1: # %entry
+; CHECK-NEXT:    rldic r4, r4
+; CHECK-NEXT:    paddi r5, 0, .LJTI0_0 at PCREL, 1
+
+entry:
+  switch i32 %param, label %sw.default [
+    i32 1, label %return
+    i32 2, label %sw.bb1
+    i32 3, label %sw.bb2
+    i32 4, label %sw.bb3
+    i32 20, label %sw.bb4
+  ]
+
+sw.bb1:                                           ; preds = %entry
+  br label %return
+
+sw.bb2:                                           ; preds = %entry
+  br label %return
+
+sw.bb3:                                           ; preds = %entry
+  br label %return
+
+sw.bb4:                                           ; preds = %entry
+  br label %return
+
+sw.default:                                       ; preds = %entry
+  br label %return
+
+return:  ; preds = %entry, %sw.default, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1
+  %retval.0 = phi i32 [ -1, %sw.default ], [ 400, %sw.bb4 ], [ 16, %sw.bb3 ],
+                      [ 9, %sw.bb2 ], [ 4, %sw.bb1 ], [ %param, %entry ]
+  ret i32 %retval.0
+}
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -2551,7 +2551,9 @@
                    ConstPoolNode->getTargetFlags() == PPCII::MO_PCREL_FLAG;
   GlobalAddressSDNode *GSDN = dyn_cast<GlobalAddressSDNode>(N.getNode());
   bool Global = GSDN && GSDN->getTargetFlags() == PPCII::MO_PCREL_FLAG;
-  if (ConstPool || Global) {
+  JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(N.getNode());
+  bool JumpTable = JT && JT->getTargetFlags() == PPCII::MO_PCREL_FLAG;
+  if (ConstPool || Global || JumpTable) {
     Base = N;
     return true;
   }
@@ -2851,6 +2853,14 @@
   // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
   // The actual address of the GlobalValue is stored in the TOC.
   if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
+    if (Subtarget.hasPCRelativeMemops()) {
+      SDLoc DL(JT);
+      EVT Ty = getPointerTy(DAG.getDataLayout());
+      SDValue GA =
+          DAG.getTargetJumpTable(JT->getIndex(), Ty, PPCII::MO_PCREL_FLAG);
+      SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
+      return MatAddr;
+    }
     setUsesTOCBasePtr(DAG);
     SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
     return getTOCEntry(DAG, SDLoc(JT), GA);


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