[PATCH] D75910: [AMDGPU] Improve scheduling model for VOP3b instructions

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
foad added reviewers: rampitec, arsenm, nhaehnle.
Herald added subscribers: llvm-commits, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.
foad added a parent revision: D75909: [AMDGPU] Remove the gfx10 VALU register destination cache model.

VOP3b instructions like v_addc_u32 write vcc (an sgpr) as well as a vgpr
result. The way this was modelled made the write to vcc take an extra
micro-op, which made the whole instruction take twice as long to issue,
which is inaccurate.

Fix this by introducing a new write class that doesn't consume any
resources.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D75910

Files:
  llvm/lib/Target/AMDGPU/SISchedule.td
  llvm/lib/Target/AMDGPU/VOP2Instructions.td
  llvm/lib/Target/AMDGPU/VOP3Instructions.td
  llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
  llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
  llvm/test/CodeGen/AMDGPU/bypass-div.ll
  llvm/test/CodeGen/AMDGPU/idot4u.ll
  llvm/test/CodeGen/AMDGPU/idot8s.ll
  llvm/test/CodeGen/AMDGPU/idot8u.ll
  llvm/test/CodeGen/AMDGPU/mul.ll
  llvm/test/CodeGen/AMDGPU/sdiv.ll
  llvm/test/CodeGen/AMDGPU/sdiv64.ll
  llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
  llvm/test/CodeGen/AMDGPU/srem64.ll
  llvm/test/CodeGen/AMDGPU/udiv64.ll
  llvm/test/CodeGen/AMDGPU/urem64.ll

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