[PATCH] D75214: [MCA][WIP] Modelling CPU front-ent: Fetch stage/Instruction Byte Buffer unit/Decoder stage (PR42202)

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb added a comment.

In D75214#1911336 <https://reviews.llvm.org/D75214#1911336>, @lebedev.ri wrote:

> In D75214#1895126 <https://reviews.llvm.org/D75214#1895126>, @andreadb wrote:
>
> > we still need to keep into account that processors may implement loop caches.
>
>
> I agree this may be useful, but i currently don't believe that to be a blocker here.


It may not a blocker for your prototype. However, a proper design of this stage should allow the definition of a loop buffer in the frontend.

> We currently don't model that, and since we don't model loops at all,
>  it would be a whole new user-activatable mode.

The idea is to let users decide whether they want to simulate fetches from the processor loop cache or not. It can be desinged as a pipeline option used by a decoder stage. By default, if that option is not set, the simulation will ignore the presence of the loop cache and always assume the IC path for opcodes.
So, I am not sure I understand what you mean by "we don't model loops at all".

> I'm not sure it should be implemented in this very patch.

No problem.
Personally, I still consider this patch as "something not for review". I still want to see a proper RFC for this; requires must be discussed first.

-Andrea


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