[PATCH] D75214: [MCA][WIP] Modelling CPU front-ent: Fetch stage/Instruction Byte Buffer unit/Decoder stage (PR42202)

Sat Mar 7 12:28:14 PST 2020

lebedev.ri added a comment.

In D75214#1895126 <https://reviews.llvm.org/D75214#1895126>, @andreadb wrote:

> we still need to keep into account that processors may implement loop caches.

I agree this may be useful, but i currently don't believe that to be a blocker here.
We currently don't model that, and since we don't model loops at all,
it would be a whole new user-activatable mode.
I'm not sure it should be implemented in this very patch.

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  https://reviews.llvm.org/D75214/new/

https://reviews.llvm.org/D75214