[llvm] 7a2ab87 - [Hexagon] Fix fshl/fshr -> combine() bug identified in D75114

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-03-06T17:23:10Z
New Revision: 7a2ab876fd64a1dd9c9c99af956154eaeb727dc5

URL: https://github.com/llvm/llvm-project/commit/7a2ab876fd64a1dd9c9c99af956154eaeb727dc5
DIFF: https://github.com/llvm/llvm-project/commit/7a2ab876fd64a1dd9c9c99af956154eaeb727dc5.diff

LOG: [Hexagon] Fix fshl/fshr -> combine() bug identified in D75114

Added: 
    

Modified: 
    llvm/lib/Target/Hexagon/HexagonPatterns.td
    llvm/test/CodeGen/Hexagon/funnel-shift.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index 2bfd8d7cd4d6..cc10627955fb 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -1095,7 +1095,7 @@ def Divu64_8: SDNodeXForm<imm, [{
 // Special cases:
 let AddedComplexity = 100 in {
   def: Pat<(fshl I32:$Rs, I32:$Rt, (i32 16)),
-           (A2_combine_hl I32:$Rs, I32:$Rt)>;
+           (A2_combine_lh I32:$Rs, I32:$Rt)>;
   def: Pat<(fshl I64:$Rs, I64:$Rt, IsMul8_U3:$S),
            (S2_valignib I64:$Rs, I64:$Rt, (Divu64_8 $S))>;
 }
@@ -1129,7 +1129,7 @@ def FShr64r: OutPatFrag<(ops node:$Rs, node:$Rt, node:$Ru),
 // Special cases:
 let AddedComplexity = 100 in {
   def: Pat<(fshr I32:$Rs, I32:$Rt, (i32 16)),
-           (A2_combine_hl I32:$Rs, I32:$Rt)>;
+           (A2_combine_lh I32:$Rs, I32:$Rt)>;
   def: Pat<(fshr I64:$Rs, I64:$Rt, IsMul8_U3:$S),
            (S2_valignib I64:$Rs, I64:$Rt, (Divu8 $S))>;
 }

diff  --git a/llvm/test/CodeGen/Hexagon/funnel-shift.ll b/llvm/test/CodeGen/Hexagon/funnel-shift.ll
index 47906814c68c..b4b8f4726021 100644
--- a/llvm/test/CodeGen/Hexagon/funnel-shift.ll
+++ b/llvm/test/CodeGen/Hexagon/funnel-shift.ll
@@ -257,7 +257,7 @@ b0:
 }
 
 ; CHECK-LABEL: f30:
-; CHECK: r[[R00:[0-9]+]] = combine(r0.h,r1.l)
+; CHECK: r[[R00:[0-9]+]] = combine(r0.l,r1.h)
 define i32 @f30(i32 %a0, i32 %a1) #1 {
 b0:
   %v0 = tail call i32 @llvm.fshl.i32(i32 %a0, i32 %a1, i32 16)
@@ -265,7 +265,7 @@ b0:
 }
 
 ; CHECK-LABEL: f31:
-; CHECK: r[[R00:[0-9]+]] = combine(r0.h,r1.l)
+; CHECK: r[[R00:[0-9]+]] = combine(r0.l,r1.h)
 define i32 @f31(i32 %a0, i32 %a1) #1 {
 b0:
   %v0 = tail call i32 @llvm.fshr.i32(i32 %a0, i32 %a1, i32 16)