[llvm] f78b9a3 - [Hexagon] Add fshl/fshr -> combine() tests identified in D75114

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2020-03-06T17:23:10Z
New Revision: f78b9a33985c9173fc7d14166a6500248b743c2c

URL: https://github.com/llvm/llvm-project/commit/f78b9a33985c9173fc7d14166a6500248b743c2c
DIFF: https://github.com/llvm/llvm-project/commit/f78b9a33985c9173fc7d14166a6500248b743c2c.diff

LOG: [Hexagon] Add fshl/fshr -> combine() tests identified in D75114

Added tests showing that the fshl/fshr -> combine() is working the wrong way around

Added: 
    

Modified: 
    llvm/test/CodeGen/Hexagon/funnel-shift.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/Hexagon/funnel-shift.ll b/llvm/test/CodeGen/Hexagon/funnel-shift.ll
index fcf623f1cec3..47906814c68c 100644
--- a/llvm/test/CodeGen/Hexagon/funnel-shift.ll
+++ b/llvm/test/CodeGen/Hexagon/funnel-shift.ll
@@ -256,6 +256,22 @@ b0:
   ret i64 %v0
 }
 
+; CHECK-LABEL: f30:
+; CHECK: r[[R00:[0-9]+]] = combine(r0.h,r1.l)
+define i32 @f30(i32 %a0, i32 %a1) #1 {
+b0:
+  %v0 = tail call i32 @llvm.fshl.i32(i32 %a0, i32 %a1, i32 16)
+  ret i32 %v0
+}
+
+; CHECK-LABEL: f31:
+; CHECK: r[[R00:[0-9]+]] = combine(r0.h,r1.l)
+define i32 @f31(i32 %a0, i32 %a1) #1 {
+b0:
+  %v0 = tail call i32 @llvm.fshr.i32(i32 %a0, i32 %a1, i32 16)
+  ret i32 %v0
+}
+
 declare i32 @llvm.fshl.i32(i32, i32, i32) #0
 declare i32 @llvm.fshr.i32(i32, i32, i32) #0
 declare i64 @llvm.fshl.i64(i64, i64, i64) #0