[llvm] 37a604c - [Hexagon] Recognize undefined registers in expandPostRAPseudo
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Fri Mar 6 06:27:59 PST 2020
Author: Krzysztof Parzyszek
Date: 2020-03-06T08:27:42-06:00
New Revision: 37a604c296f52761e9b6cf2373f24aa2deaa9ff2
URL: https://github.com/llvm/llvm-project/commit/37a604c296f52761e9b6cf2373f24aa2deaa9ff2
DIFF: https://github.com/llvm/llvm-project/commit/37a604c296f52761e9b6cf2373f24aa2deaa9ff2.diff
LOG: [Hexagon] Recognize undefined registers in expandPostRAPseudo
Added:
llvm/test/CodeGen/Hexagon/expand-copyw-undef.mir
Modified:
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 2e43c3381cdd..17834ba24194 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -790,6 +790,25 @@ bool HexagonInstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
return NumInstrs <= 4;
}
+static void getLiveInRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
+ SmallVector<std::pair<MCPhysReg, const MachineOperand*>,2> Clobbers;
+ const MachineBasicBlock &B = *MI.getParent();
+ Regs.addLiveIns(B);
+ auto E = MachineBasicBlock::const_iterator(MI.getIterator());
+ for (auto I = B.begin(); I != E; ++I) {
+ Clobbers.clear();
+ Regs.stepForward(*I, Clobbers);
+ }
+}
+
+static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
+ const MachineBasicBlock &B = *MI.getParent();
+ Regs.addLiveOuts(B);
+ auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
+ for (auto I = B.rbegin(); I != E; ++I)
+ Regs.stepBackward(*I);
+}
+
void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, MCRegister DestReg,
@@ -855,11 +874,15 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
return;
}
if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) {
- Register LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
- Register HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
+ LivePhysRegs LiveAtMI(HRI);
+ getLiveInRegsAt(LiveAtMI, *I);
+ Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
+ Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
+ unsigned UndefLo = getUndefRegState(!LiveAtMI.contains(SrcLo));
+ unsigned UndefHi = getUndefRegState(!LiveAtMI.contains(SrcHi));
BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
- .addReg(HiSrc, KillFlag)
- .addReg(LoSrc, KillFlag);
+ .addReg(SrcHi, KillFlag | UndefHi)
+ .addReg(SrcLo, KillFlag | UndefLo);
return;
}
if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) {
@@ -972,14 +995,6 @@ void HexagonInstrInfo::loadRegFromStackSlot(
}
}
-static void getLiveRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
- const MachineBasicBlock &B = *MI.getParent();
- Regs.addLiveOuts(B);
- auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
- for (auto I = B.rbegin(); I != E; ++I)
- Regs.stepBackward(*I);
-}
-
/// expandPostRAPseudo - This function is called for all pseudo instructions
/// that remain after register allocation. Many pseudo instructions are
/// created to help register allocation. This is the place to convert them
@@ -991,6 +1006,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
MachineFunction &MF = *MBB.getParent();
MachineRegisterInfo &MRI = MF.getRegInfo();
const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
+ LivePhysRegs LiveIn(HRI), LiveOut(HRI);
DebugLoc DL = MI.getDebugLoc();
unsigned Opc = MI.getOpcode();
@@ -1038,10 +1054,15 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
case Hexagon::V6_vassignp: {
Register SrcReg = MI.getOperand(1).getReg();
Register DstReg = MI.getOperand(0).getReg();
+ Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
+ Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
+ getLiveInRegsAt(LiveIn, MI);
+ unsigned UndefLo = getUndefRegState(!LiveIn.contains(SrcLo));
+ unsigned UndefHi = getUndefRegState(!LiveIn.contains(SrcHi));
unsigned Kill = getKillRegState(MI.getOperand(1).isKill());
BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
- .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill)
- .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo), Kill);
+ .addReg(SrcHi, UndefHi)
+ .addReg(SrcLo, Kill | UndefLo);
MBB.erase(MI);
return true;
}
@@ -1261,9 +1282,8 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
const MachineOperand &Op1 = MI.getOperand(1);
const MachineOperand &Op2 = MI.getOperand(2);
const MachineOperand &Op3 = MI.getOperand(3);
- LivePhysRegs LiveAtMI(HRI);
- getLiveRegsAt(LiveAtMI, MI);
- bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
+ getLiveOutRegsAt(LiveOut, MI);
+ bool IsDestLive = !LiveOut.available(MRI, Op0.getReg());
Register PReg = Op1.getReg();
assert(Op1.getSubReg() == 0);
unsigned PState = getRegState(Op1);
@@ -1295,9 +1315,8 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
MachineOperand &Op1 = MI.getOperand(1);
MachineOperand &Op2 = MI.getOperand(2);
MachineOperand &Op3 = MI.getOperand(3);
- LivePhysRegs LiveAtMI(HRI);
- getLiveRegsAt(LiveAtMI, MI);
- bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
+ getLiveOutRegsAt(LiveOut, MI);
+ bool IsDestLive = !LiveOut.available(MRI, Op0.getReg());
Register PReg = Op1.getReg();
assert(Op1.getSubReg() == 0);
unsigned PState = getRegState(Op1);
diff --git a/llvm/test/CodeGen/Hexagon/expand-copyw-undef.mir b/llvm/test/CodeGen/Hexagon/expand-copyw-undef.mir
new file mode 100644
index 000000000000..d454f1a38f19
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/expand-copyw-undef.mir
@@ -0,0 +1,16 @@
+# RUN: llc -march=hexagon -run-pass postrapseudos -run-pass machineverifier -o - %s | FileCheck %s
+
+# Check that v3 is marked as "undef".
+# CHECK: $w0 = V6_vcombine undef $v3, $v2
+
+---
+name: fred
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $w1
+ A2_nop implicit killed $v3
+ $w0 = COPY $w1
+ J2_jumpr $r31, implicit-def $pc
+...
+
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