[PATCH] D75515: [RISCV] Add new SchedRead and SchedWrite

Hsiangkai Wang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Mar 5 00:03:21 PST 2020


HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoD.td:117-120
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPALUD_rr_no_sched<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR64:$rd),
+              (ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">;
----------------
There is no need to create this class. You could remove `Sched` from `FPALUD_rr` class.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoF.td:152-155
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPALUS_rr_no_sched<bits<7> funct7, bits<3> funct3, string opcodestr>
+    : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR32:$rd),
+              (ins FPR32:$rs1, FPR32:$rs2), opcodestr, "$rd, $rs1, $rs2">;
----------------
No need to create this class. Remove `Sched` from `FPALUS_rr`.


================
Comment at: llvm/lib/Target/RISCV/RISCVSchedRocket32.td:92-93
 def : WriteRes<WriteFALU32, [Rocket32UnitFPALU]> { let Latency = 4; }
+def : WriteRes<WriteFSGNJ32, [Rocket32UnitFPALU]> { let Latency = 4; }
+def : WriteRes<WriteFMinMax32, [Rocket32UnitFPALU]> { let Latency = 4; }
 
----------------
let Latency = 4 in { ...


================
Comment at: llvm/lib/Target/RISCV/RISCVSchedRocket32.td:97-98
 def : WriteRes<WriteFALU64, [Rocket32UnitFPALU]> { let Latency = 6; }
+def : WriteRes<WriteFSGNJ64, [Rocket32UnitFPALU]> { let Latency = 6; }
+def : WriteRes<WriteFMinMax64, [Rocket32UnitFPALU]> { let Latency = 6; }
 
----------------
let Latency = 6 in { ...


================
Comment at: llvm/lib/Target/RISCV/RISCVSchedRocket64.td:105-106
 def : WriteRes<WriteFALU32, [Rocket64UnitFPALU]> { let Latency = 4; }
+def : WriteRes<WriteFSGNJ32, [Rocket64UnitFPALU]> { let Latency = 4; }
+def : WriteRes<WriteFMinMax32, [Rocket64UnitFPALU]> { let Latency = 4; }
 
----------------
let Latency = 4 in { ...


================
Comment at: llvm/lib/Target/RISCV/RISCVSchedRocket64.td:110-111
 def : WriteRes<WriteFALU64, [Rocket64UnitFPALU]> { let Latency = 6; }
+def : WriteRes<WriteFSGNJ64, [Rocket64UnitFPALU]> { let Latency = 6; }
+def : WriteRes<WriteFMinMax64, [Rocket64UnitFPALU]> { let Latency = 6; }
 
----------------
let Latency = 6 in { ...


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75515/new/

https://reviews.llvm.org/D75515





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