[PATCH] D75515: [RISCV] Add new SchedRead and SchedWrite

[Shiva Chen via Phabricator via llvm-commits]

shiva0217 created this revision.
shiva0217 added reviewers: HsiangKai, evandro, asb, lenary, luismarques.
Herald added subscribers: apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
Herald added a project: LLVM.

The patch fixes some typos and introduces ReadFMemBase, ReadFSGNJ32, ReadFSGNJ64, WriteFSGNJ32, WriteFSGNJ64, ReadFMinMax32, ReadFMinMax64, WriteFMinMax32, WriteFMinMax64, so the target CPU with different pipeline model could use them to describe latency.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D75515

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVSchedRocket32.td
  llvm/lib/Target/RISCV/RISCVSchedRocket64.td
  llvm/lib/Target/RISCV/RISCVSchedule.td

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