[llvm] 2f4f8fc - [X86] Don't add DELETED_NODES to DAG combine worklist after calling SimplifyDemandedBits/SimplifyDemandedVectorElts.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 1 00:20:32 PST 2020
Author: Craig Topper
Date: 2020-03-01T00:06:32-08:00
New Revision: 2f4f8fcf64c67ee327e19b74a82a2330cfb32312
URL: https://github.com/llvm/llvm-project/commit/2f4f8fcf64c67ee327e19b74a82a2330cfb32312
DIFF: https://github.com/llvm/llvm-project/commit/2f4f8fcf64c67ee327e19b74a82a2330cfb32312.diff
LOG: [X86] Don't add DELETED_NODES to DAG combine worklist after calling SimplifyDemandedBits/SimplifyDemandedVectorElts.
These AddToWorklist calls were added in 84cd968f75bbd6e0fbabecc29d2c1090263adec7.
It's possible the SimplifyDemandedBits/SimplifyDemandedVectorElts
triggered CSE that deleted N. Detect that and avoid adding N
to the worklist.
Fixes PR45067.
Added:
llvm/test/CodeGen/X86/pr45067.ll
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 956f57d97f0d..4c3fd0d75e78 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -42212,7 +42212,8 @@ static SDValue combineMaskedStore(SDNode *N, SelectionDAG &DAG,
if (Mask.getScalarValueSizeInBits() != 1) {
APInt DemandedBits(APInt::getSignMask(VT.getScalarSizeInBits()));
if (TLI.SimplifyDemandedBits(Mask, DemandedBits, DCI)) {
- DCI.AddToWorklist(N);
+ if (N->getOpcode() != ISD::DELETED_NODE)
+ DCI.AddToWorklist(N);
return SDValue(N, 0);
}
if (SDValue NewMask =
@@ -42479,7 +42480,8 @@ static SDValue combineVEXTRACT_STORE(SDNode *N, SelectionDAG &DAG,
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
if (TLI.SimplifyDemandedVectorElts(StoredVal, DemandedElts, KnownUndef,
KnownZero, DCI)) {
- DCI.AddToWorklist(N);
+ if (N->getOpcode() != ISD::DELETED_NODE)
+ DCI.AddToWorklist(N);
return SDValue(N, 0);
}
@@ -43828,7 +43830,8 @@ static SDValue combineBT(SDNode *N, SelectionDAG &DAG,
unsigned BitWidth = N1.getValueSizeInBits();
APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
if (DAG.getTargetLoweringInfo().SimplifyDemandedBits(N1, DemandedMask, DCI)) {
- DCI.AddToWorklist(N);
+ if (N->getOpcode() != ISD::DELETED_NODE)
+ DCI.AddToWorklist(N);
return SDValue(N, 0);
}
@@ -43846,7 +43849,8 @@ static SDValue combineCVTPH2PS(SDNode *N, SelectionDAG &DAG,
APInt DemandedElts = APInt::getLowBitsSet(8, 4);
if (TLI.SimplifyDemandedVectorElts(Src, DemandedElts, KnownUndef, KnownZero,
DCI)) {
- DCI.AddToWorklist(N);
+ if (N->getOpcode() != ISD::DELETED_NODE)
+ DCI.AddToWorklist(N);
return SDValue(N, 0);
}
@@ -44755,7 +44759,8 @@ static SDValue combineX86GatherScatter(SDNode *N, SelectionDAG &DAG,
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
APInt DemandedMask(APInt::getSignMask(Mask.getScalarValueSizeInBits()));
if (TLI.SimplifyDemandedBits(Mask, DemandedMask, DCI)) {
- DCI.AddToWorklist(N);
+ if (N->getOpcode() != ISD::DELETED_NODE)
+ DCI.AddToWorklist(N);
return SDValue(N, 0);
}
}
@@ -44847,7 +44852,8 @@ static SDValue combineGatherScatter(SDNode *N, SelectionDAG &DAG,
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
APInt DemandedMask(APInt::getSignMask(Mask.getScalarValueSizeInBits()));
if (TLI.SimplifyDemandedBits(Mask, DemandedMask, DCI)) {
- DCI.AddToWorklist(N);
+ if (N->getOpcode() != ISD::DELETED_NODE)
+ DCI.AddToWorklist(N);
return SDValue(N, 0);
}
}
diff --git a/llvm/test/CodeGen/X86/pr45067.ll b/llvm/test/CodeGen/X86/pr45067.ll
new file mode 100644
index 000000000000..fc1baa3d56dd
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr45067.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skylake | FileCheck %s
+
+ at global = external global i32, align 4
+
+define void @foo(<8 x i32>* %x, <8 x i1> %y) {
+; CHECK-LABEL: foo:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
+; CHECK-NEXT: vpbroadcastq _global@{{.*}}(%rip), %ymm2
+; CHECK-NEXT: vpgatherqd %xmm1, (,%ymm2), %xmm3
+; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; CHECK-NEXT: vpslld $31, %ymm0, %ymm0
+; CHECK-NEXT: vinserti128 $1, %xmm3, %ymm3, %ymm1
+; CHECK-NEXT: vpmaskmovd %ymm1, %ymm0, (%rdi)
+; CHECK-NEXT: ud2
+ %tmp = call <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*> <i32* @global, i32* @global, i32* @global, i32* @global, i32* @global, i32* @global, i32* @global, i32* @global>, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i32> undef)
+ call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %tmp, <8 x i32>* %x, i32 4, <8 x i1> %y)
+ unreachable
+}
+
+declare <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*>, i32, <8 x i1>, <8 x i32>)
+declare void @llvm.masked.store.v8i32.p0v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>)
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