[PATCH] D75359: [BranchAlign] Fix bug w/nop padding for SS manipulation

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
reames added reviewers: skan, craig.topper, annita.zhang, jyknight.
Herald added subscribers: bollu, hiraditya, mcrosier.
Herald added a project: LLVM.

X86 has several instructions which are documented as enabling interrupts exactly one instruction *after* the one which changes the SS segment register.  Inserting a nop between these two instructions allows an interrupt to arrive before the execution of the following instruction which changes semantic behaviour.

The list of instructions is documented in "Table 24-3. Format of Interruptibility State" in Volume 3c of the Intel manual.  They basically all come down to different ways to write to the SS register.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D75359

Files:
  llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
  llvm/test/MC/X86/align-branch-64-system.s

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