[PATCH] D74937: [AMDGPU] Implement copyPhysReg for 16 bit subregs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:717
+    auto First = BuildMI(MBB, &*Last, DL, get(OpcFirst), DestReg);
+    if (DstLow == SrcLow) // alignbyte
+      First.addReg(SrcLow ? SrcReg : DestReg,
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Braecss


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:723
+           .addImm(2);
+    else
+      First.addImm(16)
----------------
Braecs


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Comment at: llvm/test/CodeGen/AMDGPU/lo16-hi16-physreg-copy.mir:105
+    S_ENDPGM 0
+...
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Needs some tests with both halves in the same 32-bit register

Also need some with kill and undef flag handling


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74937/new/

https://reviews.llvm.org/D74937