[llvm] 970558d - [AMDGPU] Mark the scheduling model as complete

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2020-02-28T13:35:55Z
New Revision: 970558df94be1579c6ad95c7ea4ac19bd951fd3e

URL: https://github.com/llvm/llvm-project/commit/970558df94be1579c6ad95c7ea4ac19bd951fd3e
DIFF: https://github.com/llvm/llvm-project/commit/970558df94be1579c6ad95c7ea4ac19bd951fd3e.diff

LOG: [AMDGPU] Mark the scheduling model as complete

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SISchedule.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SISchedule.td b/llvm/lib/Target/AMDGPU/SISchedule.td
index 824d1aeb0df9..c512569b9b32 100644
--- a/llvm/lib/Target/AMDGPU/SISchedule.td
+++ b/llvm/lib/Target/AMDGPU/SISchedule.td
@@ -56,7 +56,7 @@ def Write16PassMAI : SchedWrite;
 // instructions)
 
 class SISchedMachineModel : SchedMachineModel {
-  let CompleteModel = 0;
+  let CompleteModel = 1;
   // MicroOpBufferSize = 1 means that instructions will always be added
   // the ready queue when they become available.  This exposes them
   // to the register pressure analysis.