[PATCH] D75273: [entry values] ARM: Add a describeLoadedValue override (PR45025)

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Oh, now I see what's happening, I think.  We're trying to get a description of some double register (like d8).  We find the VMOVS because it "defines" d8.  But even though VMOVS is a COPY, it's a COPY defining s17, not d8.  (Actually, I think there's a missing implicit use, since it's combining s16 and s17 to produce d8.)

Given that, I guess this is the right fix.

This is sort of similar to what the AArch64 code is doing, but not really.  There, the high bits are implicitly zeroed, so we don't need to worry about finding some other instruction.  Here, we would actually have to merge the definition of s16 with the definition of s17 to produce anything useful.



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Comment at: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp:1040
+    Register DstReg = CopyDst.getReg();
+    if (TRI->isSuperRegister(Reg, DstReg) || TRI->isSubRegister(Reg, DstReg))
+      return None;
----------------
Could you simplify this to just `if (DstReg != Reg)`?


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  https://reviews.llvm.org/D75273/new/

https://reviews.llvm.org/D75273