[PATCH] D75079: Update LSR's logic that identifies a post-increment SCEV value.

[Brendon Cahoon via Phabricator via llvm-commits]

bcahoon added inline comments.


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Comment at: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:3535
-      LoopStep->getType()->getScalarSizeInBits())
-    return false;
   // Check if a post-indexed load/store can be used.
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I don't remember why I added that code. It doesn't make any sense to me, so I think it's good to remove.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75079/new/

https://reviews.llvm.org/D75079