[PATCH] D75079: Update LSR's logic that identifies a post-increment SCEV value.

[Sumanth Gundapaneni via Phabricator via llvm-commits]

sgundapa created this revision.
sgundapa added reviewers: kparzysz, bcahoon, qcolombet.
Herald added subscribers: llvm-commits, dmgreen, hiraditya.
Herald added a project: LLVM.

One of the checks has been removed as it seem invalid.
The LoopStep size is always almost a 32-bit.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D75079

Files:
  llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
  llvm/test/CodeGen/Hexagon/addrmode-align.ll
  llvm/test/CodeGen/Hexagon/lsr-postinc-nested-loop.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll

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