[PATCH] D75079: Update LSR's logic that identifies a post-increment SCEV value.
Sumanth Gundapaneni via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 24 14:20:19 PST 2020
sgundapa created this revision.
sgundapa added reviewers: kparzysz, bcahoon, qcolombet.
Herald added subscribers: llvm-commits, dmgreen, hiraditya.
Herald added a project: LLVM.
One of the checks has been removed as it seem invalid.
The LoopStep size is always almost a 32-bit.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D75079
Files:
llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
llvm/test/CodeGen/Hexagon/addrmode-align.ll
llvm/test/CodeGen/Hexagon/lsr-postinc-nested-loop.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D75079.246303.patch
Type: text/x-patch
Size: 16650 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200224/ed82b125/attachment.bin>
More information about the llvm-commits
mailing list