[PATCH] D75086: [AArch64][GlobalISel] Fixup <32b heterogeneous regbanks of G_PHIs just before selection.

[Amara Emerson via Phabricator via llvm-commits]

aemerson added a comment.

In D75086#1893996 <https://reviews.llvm.org/D75086#1893996>, @qcolombet wrote:

> Thanks for the clarification Amara.
>
> Now a follow-up question:
>
> > If this happens, the PHI operand with a GPR RegBank gets the gpr32 regclass assigned to it (we don't have anything smaller to represent types like s16 on GPR on AArch64).
>
> How do you represent s16 values into gpr32?


s16 operations, if legal, just get selected to gpr32 regclass instructions. E.g.

  %ld:gpr(s16) = G_LOAD ...
  =>
  %ld:gpr32 = LDR_16 ...

For things like G_ADD we legalize to s32, but s16 itself as a type isn't illegal.

> I would have expected that if you have to widen the size when assigning the actual register class, then legalization should have actually widen the value. Otherwise, that means we have to manually deal with "dangling" bits everywhere else.




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