[PATCH] D74471: [AArch64][SVE] Add predicate reinterpret intrinsics

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes updated this revision to Diff 246163.
c-rhodes marked an inline comment as done.
c-rhodes added a comment.

Remove change to lower `SPLAT_VECTOR` of i1s to `pfalse` and update test.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74471/new/

https://reviews.llvm.org/D74471

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll

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