[PATCH] D75030: [AMDGPU] Use conservative defaults for XNACK/SRAM ECC

Austin Kerbow via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Feb 23 23:12:33 PST 2020 

kerbowa created this revision.
kerbowa added reviewers: rampitec, arsenm, t-tye, kzhuravl, nhaehnle.
Herald added subscribers: llvm-commits, asbirlea, jfb, arphaman, hiraditya, tpr, dstuttard, yaxunl, wdng, jvesely, qcolombet.
Herald added a project: LLVM.

RFC. WIP. Use conservatively correct settings for XNACK and SRAM ECC for all
subtargets which may support either feature. The conservative settings
in this case are XNACK on and SRAM ECC on.

Although some additional updates must be completed outside of the
backend to facilitate this change, I'm posting this review now for
visibility.

Change-Id: I158e5bf8bb6869dea147e875f562a2fe290fbf80


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D75030

Files:
  llvm/lib/Target/AMDGPU/AMDGPU.td
  llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.gws.barrier.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
  llvm/test/CodeGen/AMDGPU/add.i16.ll
  llvm/test/CodeGen/AMDGPU/add.v2i16.ll
  llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fold-binop-select.ll
  llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
  llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
  llvm/test/CodeGen/AMDGPU/amdhsa-trap-num-sgprs.ll
  llvm/test/CodeGen/AMDGPU/and.ll
  llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
  llvm/test/CodeGen/AMDGPU/atomicrmw-nand.ll
  llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-v3.ll
  llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll
  llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll
  llvm/test/CodeGen/AMDGPU/attr-amdgpu-waves-per-eu.ll
  llvm/test/CodeGen/AMDGPU/bitcast-vector-extract.ll
  llvm/test/CodeGen/AMDGPU/bitreverse.ll
  llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir
  llvm/test/CodeGen/AMDGPU/break-vmem-soft-clauses.mir
  llvm/test/CodeGen/AMDGPU/bswap.ll
  llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll
  llvm/test/CodeGen/AMDGPU/call-argument-types.ll
  llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
  llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
  llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
  llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
  llvm/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir
  llvm/test/CodeGen/AMDGPU/code-object-v3.ll
  llvm/test/CodeGen/AMDGPU/commute-shifts.ll
  llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
  llvm/test/CodeGen/AMDGPU/constant-fold-mi-operands.ll
  llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
  llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
  llvm/test/CodeGen/AMDGPU/ctlz.ll
  llvm/test/CodeGen/AMDGPU/ctpop16.ll
  llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
  llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
  llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
  llvm/test/CodeGen/AMDGPU/elf-header-flags-sram-ecc.ll
  llvm/test/CodeGen/AMDGPU/elf-header-flags-xnack.ll
  llvm/test/CodeGen/AMDGPU/elf-notes.ll
  llvm/test/CodeGen/AMDGPU/exceed-max-sgprs.ll
  llvm/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll
  llvm/test/CodeGen/AMDGPU/fabs.ll
  llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
  llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll
  llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll
  llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
  llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
  llvm/test/CodeGen/AMDGPU/fneg-combines.ll
  llvm/test/CodeGen/AMDGPU/fneg-fabs.ll
  llvm/test/CodeGen/AMDGPU/function-returns.ll
  llvm/test/CodeGen/AMDGPU/global-saddr.ll
  llvm/test/CodeGen/AMDGPU/global_smrd_cfg.ll
  llvm/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir
  llvm/test/CodeGen/AMDGPU/hazard-in-bundle.mir
  llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props-v3.ll
  llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll
  llvm/test/CodeGen/AMDGPU/idiv-licm.ll
  llvm/test/CodeGen/AMDGPU/idot2.ll
  llvm/test/CodeGen/AMDGPU/idot4s.ll
  llvm/test/CodeGen/AMDGPU/idot4u.ll
  llvm/test/CodeGen/AMDGPU/idot8s.ll
  llvm/test/CodeGen/AMDGPU/idot8u.ll
  llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll
  llvm/test/CodeGen/AMDGPU/imm.ll
  llvm/test/CodeGen/AMDGPU/imm16.ll
  llvm/test/CodeGen/AMDGPU/immv216.ll
  llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
  llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
  llvm/test/CodeGen/AMDGPU/lds-branch-vmem-hazard.mir
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ubfe.ll
  llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll
  llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
  llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
  llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
  llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll
  llvm/test/CodeGen/AMDGPU/load-hi16.ll
  llvm/test/CodeGen/AMDGPU/load-lo16.ll
  llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
  llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll
  llvm/test/CodeGen/AMDGPU/mad_uint24.ll
  llvm/test/CodeGen/AMDGPU/max.i16.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-cmpxchg.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-rmw.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-load.ll
  llvm/test/CodeGen/AMDGPU/memory-legalizer-store.ll
  llvm/test/CodeGen/AMDGPU/min.ll
  llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
  llvm/test/CodeGen/AMDGPU/mul_int24.ll
  llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
  llvm/test/CodeGen/AMDGPU/nested-calls.ll
  llvm/test/CodeGen/AMDGPU/nsa-reassign.ll
  llvm/test/CodeGen/AMDGPU/nsa-vmem-hazard.mir
  llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
  llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
  llvm/test/CodeGen/AMDGPU/offset-split-global.ll
  llvm/test/CodeGen/AMDGPU/or.ll
  llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll
  llvm/test/CodeGen/AMDGPU/s_addk_i32.ll
  llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
  llvm/test/CodeGen/AMDGPU/saddo.ll
  llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
  llvm/test/CodeGen/AMDGPU/scratch-simple.ll
  llvm/test/CodeGen/AMDGPU/sdiv.ll
  llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll
  llvm/test/CodeGen/AMDGPU/select-vectors.ll
  llvm/test/CodeGen/AMDGPU/select.f16.ll
  llvm/test/CodeGen/AMDGPU/setcc-limit-load-shrink.ll
  llvm/test/CodeGen/AMDGPU/setcc-opt.ll
  llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
  llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
  llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
  llvm/test/CodeGen/AMDGPU/sibling-call.ll
  llvm/test/CodeGen/AMDGPU/sign_extend.ll
  llvm/test/CodeGen/AMDGPU/smed3.ll
  llvm/test/CodeGen/AMDGPU/smrd.ll
  llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
  llvm/test/CodeGen/AMDGPU/sram-ecc-default.ll
  llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
  llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll
  llvm/test/CodeGen/AMDGPU/stack-realign.ll
  llvm/test/CodeGen/AMDGPU/store-hi16.ll
  llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
  llvm/test/CodeGen/AMDGPU/sub.i16.ll
  llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
  llvm/test/CodeGen/AMDGPU/trunc-combine.ll
  llvm/test/CodeGen/AMDGPU/umed3.ll
  llvm/test/CodeGen/AMDGPU/v_madak_f16.ll
  llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
  llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
  llvm/test/CodeGen/AMDGPU/vmem-vcc-hazard.mir
  llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
  llvm/test/CodeGen/AMDGPU/wave32.ll
  llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
  llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
  llvm/test/CodeGen/AMDGPU/xor.ll
  llvm/test/CodeGen/AMDGPU/zero_extend.ll
  llvm/test/MC/AMDGPU/hsa-sgpr-init-bug-v3.s
  llvm/test/MC/AMDGPU/isa-version-hsa.s
  llvm/test/MC/AMDGPU/isa-version-pal.s
  llvm/test/MC/AMDGPU/isa-version-unk.s
  llvm/test/MC/AMDGPU/reg-syntax-err.s
  llvm/test/MC/AMDGPU/xnack-mask.s

More information about the llvm-commits mailing list