[PATCH] D74471: [AArch64][SVE] Add predicate reinterpret intrinsics

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Looks fine other than the change to LowerSPLAT_VECTOR



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7481
+      if (CSplatVal->isNullValue())
+        return SDValue(DAG.getMachineNode(AArch64::PFALSE, dl, VT), 0);
     // The general case of i1.  There isn't any natural way to do this,
----------------
We should not be calling getMachineNode before Select().  If we need a new AArch64ISD opcode, please add one.

I'm not sure how this is relevant to the rest of the patch, in any case.


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  https://reviews.llvm.org/D74471/new/

https://reviews.llvm.org/D74471