[llvm] 78be618 - [X86] Add CMOV_VR64 pseudo instruction for MMX. Remove mmx handling from combineSelect.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2020-02-20T20:30:56-08:00
New Revision: 78be61871704a451a5d9462d7e96ed6c982746d4

URL: https://github.com/llvm/llvm-project/commit/78be61871704a451a5d9462d7e96ed6c982746d4
DIFF: https://github.com/llvm/llvm-project/commit/78be61871704a451a5d9462d7e96ed6c982746d4.diff

LOG: [X86] Add CMOV_VR64 pseudo instruction for MMX. Remove mmx handling from combineSelect.

The combineSelect code was casting to i64 without any check that
i64 was legal. This can break after type legalization.

It also required splitting the mmx register on 32-bit targets.
It's not clear that this makes sense. Instead switch to using
a cmov pseudo like we do for XMM/YMM/ZMM.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/lib/Target/X86/X86InstrCompiler.td
    llvm/test/CodeGen/X86/select-mmx.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 74583efddb8e..f0e40fd47de8 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -30944,6 +30944,7 @@ static bool isCMOVPseudo(MachineInstr &MI) {
   case X86::CMOV_RFP32:
   case X86::CMOV_RFP64:
   case X86::CMOV_RFP80:
+  case X86::CMOV_VR64:
   case X86::CMOV_VR128:
   case X86::CMOV_VR128X:
   case X86::CMOV_VR256:
@@ -32586,6 +32587,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
   case X86::CMOV_RFP32:
   case X86::CMOV_RFP64:
   case X86::CMOV_RFP80:
+  case X86::CMOV_VR64:
   case X86::CMOV_VR128:
   case X86::CMOV_VR128X:
   case X86::CMOV_VR256:
@@ -38861,14 +38863,6 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
       return DAG.getNode(N->getOpcode(), DL, VT,
                          DAG.getBitcast(CondVT, CondNot), RHS, LHS);
 
-  // Custom action for SELECT MMX
-  if (VT == MVT::x86mmx) {
-    LHS = DAG.getBitcast(MVT::i64, LHS);
-    RHS = DAG.getBitcast(MVT::i64, RHS);
-    SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::i64, Cond, LHS, RHS);
-    return DAG.getBitcast(VT, newSelect);
-  }
-
   // Try to optimize vXi1 selects if both operands are either all constants or
   // bitcasts from scalar integer type. In that case we can convert the operands
   // to integer and use an integer select which will be converted to a CMOV.

diff  --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td
index c3300e0e97f5..fe1efd2fc097 100644
--- a/llvm/lib/Target/X86/X86InstrCompiler.td
+++ b/llvm/lib/Target/X86/X86InstrCompiler.td
@@ -531,10 +531,13 @@ let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Uses = [EFLAGS] in {
 
   defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>;
 
-  let Predicates = [NoAVX512] in {
+  let Predicates = [HasMMX] in
+    defm _VR64   : CMOVrr_PSEUDO<VR64, x86mmx>;
+
+  let Predicates = [HasSSE1,NoAVX512] in
     defm _FR32   : CMOVrr_PSEUDO<FR32, f32>;
+  let Predicates = [HasSSE2,NoAVX512] in
     defm _FR64   : CMOVrr_PSEUDO<FR64, f64>;
-  }
   let Predicates = [HasAVX512] in {
     defm _FR32X  : CMOVrr_PSEUDO<FR32X, f32>;
     defm _FR64X  : CMOVrr_PSEUDO<FR64X, f64>;

diff  --git a/llvm/test/CodeGen/X86/select-mmx.ll b/llvm/test/CodeGen/X86/select-mmx.ll
index da00f0f328e9..f6bd4adb02b4 100644
--- a/llvm/test/CodeGen/X86/select-mmx.ll
+++ b/llvm/test/CodeGen/X86/select-mmx.ll
@@ -14,11 +14,15 @@ define i64 @test47(i64 %arg)  {
 ;
 ; X64-LABEL: test47:
 ; X64:       # %bb.0:
-; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    testq %rdi, %rdi
-; X64-NEXT:    movl $7, %ecx
-; X64-NEXT:    cmovneq %rax, %rcx
-; X64-NEXT:    movq %rcx, %mm0
+; X64-NEXT:    je .LBB0_1
+; X64-NEXT:  # %bb.2:
+; X64-NEXT:    pxor %mm0, %mm0
+; X64-NEXT:    jmp .LBB0_3
+; X64-NEXT:  .LBB0_1:
+; X64-NEXT:    movl $7, %eax
+; X64-NEXT:    movd %eax, %mm0
+; X64-NEXT:  .LBB0_3:
 ; X64-NEXT:    psllw %mm0, %mm0
 ; X64-NEXT:    movq %mm0, %rax
 ; X64-NEXT:    retq
@@ -31,17 +35,17 @@ define i64 @test47(i64 %arg)  {
 ; I32-NEXT:    movl %esp, %ebp
 ; I32-NEXT:    .cfi_def_cfa_register %ebp
 ; I32-NEXT:    andl $-8, %esp
-; I32-NEXT:    subl $16, %esp
+; I32-NEXT:    subl $8, %esp
 ; I32-NEXT:    movl 8(%ebp), %eax
 ; I32-NEXT:    orl 12(%ebp), %eax
+; I32-NEXT:    je .LBB0_1
+; I32-NEXT:  # %bb.2:
+; I32-NEXT:    pxor %mm0, %mm0
+; I32-NEXT:    jmp .LBB0_3
+; I32-NEXT:  .LBB0_1:
 ; I32-NEXT:    movl $7, %eax
-; I32-NEXT:    je .LBB0_2
-; I32-NEXT:  # %bb.1:
-; I32-NEXT:    xorl %eax, %eax
-; I32-NEXT:  .LBB0_2:
-; I32-NEXT:    movl %eax, {{[0-9]+}}(%esp)
-; I32-NEXT:    movl $0, {{[0-9]+}}(%esp)
-; I32-NEXT:    movq {{[0-9]+}}(%esp), %mm0
+; I32-NEXT:    movd %eax, %mm0
+; I32-NEXT:  .LBB0_3:
 ; I32-NEXT:    psllw %mm0, %mm0
 ; I32-NEXT:    movq %mm0, (%esp)
 ; I32-NEXT:    movl (%esp), %eax
@@ -70,8 +74,13 @@ define i64 @test49(i64 %arg, i64 %x, i64 %y) {
 ; X64-LABEL: test49:
 ; X64:       # %bb.0:
 ; X64-NEXT:    testq %rdi, %rdi
-; X64-NEXT:    cmovneq %rdx, %rsi
+; X64-NEXT:    je .LBB1_1
+; X64-NEXT:  # %bb.2:
+; X64-NEXT:    movq %rdx, %mm0
+; X64-NEXT:    jmp .LBB1_3
+; X64-NEXT:  .LBB1_1:
 ; X64-NEXT:    movq %rsi, %mm0
+; X64-NEXT:  .LBB1_3:
 ; X64-NEXT:    psllw %mm0, %mm0
 ; X64-NEXT:    movq %mm0, %rax
 ; X64-NEXT:    retq