[PATCH] D74804: AMDGPU: Use undef_tied_input on VOP3P instructions
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 18 15:53:25 PST 2020
arsenm created this revision.
arsenm added a reviewer: rampitec.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.
arsenm added a parent revision: D74803: TableGen: Fix logic for default operands.
In a future commit this will help simplify patterns.
https://reviews.llvm.org/D74804
Files:
llvm/lib/Target/AMDGPU/SIInstrInfo.td
llvm/lib/Target/AMDGPU/VOP3PInstructions.td
Index: llvm/lib/Target/AMDGPU/VOP3PInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -10,6 +10,9 @@
// VOP3P Classes
//===----------------------------------------------------------------------===//
+class vdst_in_op32<ValueType vt> :
+ OperandWithDefaultOps<vt, (VGPR_32 undef_tied_input)>;
+
class VOP3PInst<string OpName, VOPProfile P, SDPatternOperator node = null_frag> :
VOP3P_Pseudo<OpName, P,
!if(P.HasModifiers, getVOP3PModPat<P, node>.ret, getVOP3Pat<P, node>.ret)
@@ -31,7 +34,7 @@
FP16InputMods:$src1_modifiers, VCSrc_f16:$src1,
FP16InputMods:$src2_modifiers, VCSrc_f16:$src2,
clampmod:$clamp),
- !if(UseTiedOutput, (ins VGPR_32:$vdst_in), (ins))),
+ !if(UseTiedOutput, (ins vdst_in_op32<P.DstVT>:$vdst_in), (ins))),
(ins op_sel:$op_sel, op_sel_hi:$op_sel_hi));
let Constraints = !if(UseTiedOutput, "$vdst = $vdst_in", "");
@@ -91,7 +94,7 @@
$src1_modifiers, $src1,
$src2_modifiers, $src2,
DSTCLAMP.NONE,
- (i32 (IMPLICIT_DEF)))
+ (IMPLICIT_DEF))
>;
// FIXME: Special case handling for maxhi (especially for clamp)
@@ -137,7 +140,7 @@
$lo_src1_modifiers, $lo_src1,
$lo_src2_modifiers, $lo_src2,
DSTCLAMP.ENABLE,
- (i32 (IMPLICIT_DEF)))))
+ (IMPLICIT_DEF))))
>;
}
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.td
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -1339,8 +1339,8 @@
}
def DSTCLAMP {
- int NONE = 0;
- int ENABLE = 1;
+ bit NONE = 0;
+ bit ENABLE = 1;
}
def DSTOMOD {
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