[llvm] 58f66f8 - [ARM,CDE] Cosmetic changes, additonal driver tests
Mikhail Maltsev via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 18 02:23:17 PST 2020
Author: Mikhail Maltsev
Date: 2020-02-18T10:23:09Z
New Revision: 58f66f8af01db7f7f349654793a2b88376644122
URL: https://github.com/llvm/llvm-project/commit/58f66f8af01db7f7f349654793a2b88376644122
DIFF: https://github.com/llvm/llvm-project/commit/58f66f8af01db7f7f349654793a2b88376644122.diff
LOG: [ARM,CDE] Cosmetic changes, additonal driver tests
Summary:
This is a follow-up patch addressing post-commit comments in
https://reviews.llvm.org/D74044:
* Add more Clang driver tests (-march=armv8.1m.main and -march=armv8.1m.main+mve.fp)
* Clang-format a chunk in ARMAsmParser.cpp
* Add a missing copyright header to ARMInstrCDE.td
Reviewers: SjoerdMeijer, simon_tatham, dmgreen
Reviewed By: SjoerdMeijer
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D74732
Added:
Modified:
clang/test/Driver/arm-cde.c
llvm/lib/Target/ARM/ARMInstrCDE.td
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Removed:
################################################################################
diff --git a/clang/test/Driver/arm-cde.c b/clang/test/Driver/arm-cde.c
index 696bee46cc34..8dfa130da3fb 100644
--- a/clang/test/Driver/arm-cde.c
+++ b/clang/test/Driver/arm-cde.c
@@ -1,5 +1,7 @@
-// RUN: %clang -target arm-none-none-eabi -march=armv8m.main %s -### -c 2>&1 | FileCheck %s --check-prefix=CHECK-NOCDE
-// CHECK-NOCDE: "-triple" "thumbv8m.main-none-none-eabi"
+// RUN: %clang -target arm-none-none-eabi -march=armv8m.main %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-NOCDE,CHECK-NOCDE-V8
+// RUN: %clang -target arm-none-none-eabi -march=armv8.1m.main %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-NOCDE,CHECK-NOCDE-V81
+// CHECK-NOCDE-V8: "-triple" "thumbv8m.main-none-none-eabi"
+// CHECK-NOCDE-V81: "-triple" "thumbv8.1m.main-none-none-eabi"
// CHECK-NOCDE-NOT: "-target-feature" "+cdecp0"
// CHECK-NOCDE-NOT: "-target-feature" "+cdecp1"
// CHECK-NOCDE-NOT: "-target-feature" "+cdecp2"
@@ -9,13 +11,20 @@
// CHECK-NOCDE-NOT: "-target-feature" "+cdecp6"
// CHECK-NOCDE-NOT: "-target-feature" "+cdecp7"
-// RUN: %clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 %s -### -c 2>&1 | FileCheck %s --check-prefix=CHECK-CDE1
-// CHECK-CDE1: "-triple" "thumbv8m.main-none-none-eabi"
+// RUN: %clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-CDE1,CHECK-CDE1-V8
+// RUN: %clang -target arm-none-none-eabi -march=armv8.1m.main+cdecp0+cdecp3 %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-CDE1,CHECK-CDE1-V81
+// RUN: %clang -target arm-none-none-eabi -march=armv8.1m.main+mve.fp+cdecp0+cdecp3 %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-CDE1,CHECK-CDE1-V81MVE
+// CHECK-CDE1-V8: "-triple" "thumbv8m.main-none-none-eabi"
+// CHECK-CDE1-V81: "-triple" "thumbv8.1m.main-none-none-eabi"
+// CHECK-CDE1-V81MVE: "-triple" "thumbv8.1m.main-none-none-eabi"
+// CHECK-CDE1-V81MVE-DAG: "-target-feature" "+mve.fp"
// CHECK-CDE1-DAG: "-target-feature" "+cdecp0"
// CHECK-CDE1-DAG: "-target-feature" "+cdecp3"
-// RUN: %clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 %s -### -c 2>&1 | FileCheck %s --check-prefix=CHECK-CDE2
-// CHECK-CDE2: "-triple" "thumbv8m.main-none-none-eabi"
+// RUN: %clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-CDE2,CHECK-CDE2-V8
+// RUN: %clang -target arm-none-none-eabi -march=armv8.1m.main+cdecp0+cdecp3 %s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-CDE2,CHECK-CDE2-V81
+// CHECK-CDE2-V8: "-triple" "thumbv8m.main-none-none-eabi"
+// CHECK-CDE2-V81: "-triple" "thumbv8.1m.main-none-none-eabi"
// CHECK-CDE2-NOT: "-target-feature" "+cdecp1"
// CHECK-CDE2-NOT: "-target-feature" "+cdecp2"
// CHECK-CDE2-NOT: "-target-feature" "+cdecp4"
diff --git a/llvm/lib/Target/ARM/ARMInstrCDE.td b/llvm/lib/Target/ARM/ARMInstrCDE.td
index 4e73ea819473..fb02e9fefd8c 100644
--- a/llvm/lib/Target/ARM/ARMInstrCDE.td
+++ b/llvm/lib/Target/ARM/ARMInstrCDE.td
@@ -1,3 +1,15 @@
+//===-- ARMInstrCDE.td - CDE support for ARM ---------------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the Arm CDE (Custom Datapath Extension) instruction set.
+//
+//===----------------------------------------------------------------------===//
+
// Immediate operand of arbitrary bit width
class BitWidthImmOperand<int width>
: ImmAsmOperand<0, !add(!shl(1, width), -1)> {
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 65c2d4790633..3ffee6804b3c 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -8136,15 +8136,36 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
break;
}
- case ARM::CDE_CX1: case ARM::CDE_CX1A: case ARM::CDE_CX1D: case ARM::CDE_CX1DA:
- case ARM::CDE_CX2: case ARM::CDE_CX2A: case ARM::CDE_CX2D: case ARM::CDE_CX2DA:
- case ARM::CDE_CX3: case ARM::CDE_CX3A: case ARM::CDE_CX3D: case ARM::CDE_CX3DA:
- case ARM::CDE_VCX1_vec: case ARM::CDE_VCX1_fpsp: case ARM::CDE_VCX1_fpdp:
- case ARM::CDE_VCX1A_vec: case ARM::CDE_VCX1A_fpsp: case ARM::CDE_VCX1A_fpdp:
- case ARM::CDE_VCX2_vec: case ARM::CDE_VCX2_fpsp: case ARM::CDE_VCX2_fpdp:
- case ARM::CDE_VCX2A_vec: case ARM::CDE_VCX2A_fpsp: case ARM::CDE_VCX2A_fpdp:
- case ARM::CDE_VCX3_vec: case ARM::CDE_VCX3_fpsp: case ARM::CDE_VCX3_fpdp:
- case ARM::CDE_VCX3A_vec: case ARM::CDE_VCX3A_fpsp: case ARM::CDE_VCX3A_fpdp: {
+ case ARM::CDE_CX1:
+ case ARM::CDE_CX1A:
+ case ARM::CDE_CX1D:
+ case ARM::CDE_CX1DA:
+ case ARM::CDE_CX2:
+ case ARM::CDE_CX2A:
+ case ARM::CDE_CX2D:
+ case ARM::CDE_CX2DA:
+ case ARM::CDE_CX3:
+ case ARM::CDE_CX3A:
+ case ARM::CDE_CX3D:
+ case ARM::CDE_CX3DA:
+ case ARM::CDE_VCX1_vec:
+ case ARM::CDE_VCX1_fpsp:
+ case ARM::CDE_VCX1_fpdp:
+ case ARM::CDE_VCX1A_vec:
+ case ARM::CDE_VCX1A_fpsp:
+ case ARM::CDE_VCX1A_fpdp:
+ case ARM::CDE_VCX2_vec:
+ case ARM::CDE_VCX2_fpsp:
+ case ARM::CDE_VCX2_fpdp:
+ case ARM::CDE_VCX2A_vec:
+ case ARM::CDE_VCX2A_fpsp:
+ case ARM::CDE_VCX2A_fpdp:
+ case ARM::CDE_VCX3_vec:
+ case ARM::CDE_VCX3_fpsp:
+ case ARM::CDE_VCX3_fpdp:
+ case ARM::CDE_VCX3A_vec:
+ case ARM::CDE_VCX3A_fpsp:
+ case ARM::CDE_VCX3A_fpdp: {
assert(Inst.getOperand(1).isImm() &&
"CDE operand 1 must be a coprocessor ID");
int64_t Coproc = Inst.getOperand(1).getImm();
@@ -8157,17 +8178,48 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
break;
}
- case ARM::t2CDP: case ARM::t2CDP2:
- case ARM::t2LDC2L_OFFSET: case ARM::t2LDC2L_OPTION: case ARM::t2LDC2L_POST: case ARM::t2LDC2L_PRE:
- case ARM::t2LDC2_OFFSET: case ARM::t2LDC2_OPTION: case ARM::t2LDC2_POST: case ARM::t2LDC2_PRE:
- case ARM::t2LDCL_OFFSET: case ARM::t2LDCL_OPTION: case ARM::t2LDCL_POST: case ARM::t2LDCL_PRE:
- case ARM::t2LDC_OFFSET: case ARM::t2LDC_OPTION: case ARM::t2LDC_POST: case ARM::t2LDC_PRE:
- case ARM::t2MCR: case ARM::t2MCR2: case ARM::t2MCRR: case ARM::t2MCRR2:
- case ARM::t2MRC: case ARM::t2MRC2: case ARM::t2MRRC: case ARM::t2MRRC2:
- case ARM::t2STC2L_OFFSET: case ARM::t2STC2L_OPTION: case ARM::t2STC2L_POST: case ARM::t2STC2L_PRE:
- case ARM::t2STC2_OFFSET: case ARM::t2STC2_OPTION: case ARM::t2STC2_POST: case ARM::t2STC2_PRE:
- case ARM::t2STCL_OFFSET: case ARM::t2STCL_OPTION: case ARM::t2STCL_POST: case ARM::t2STCL_PRE:
- case ARM::t2STC_OFFSET: case ARM::t2STC_OPTION: case ARM::t2STC_POST: case ARM::t2STC_PRE: {
+ case ARM::t2CDP:
+ case ARM::t2CDP2:
+ case ARM::t2LDC2L_OFFSET:
+ case ARM::t2LDC2L_OPTION:
+ case ARM::t2LDC2L_POST:
+ case ARM::t2LDC2L_PRE:
+ case ARM::t2LDC2_OFFSET:
+ case ARM::t2LDC2_OPTION:
+ case ARM::t2LDC2_POST:
+ case ARM::t2LDC2_PRE:
+ case ARM::t2LDCL_OFFSET:
+ case ARM::t2LDCL_OPTION:
+ case ARM::t2LDCL_POST:
+ case ARM::t2LDCL_PRE:
+ case ARM::t2LDC_OFFSET:
+ case ARM::t2LDC_OPTION:
+ case ARM::t2LDC_POST:
+ case ARM::t2LDC_PRE:
+ case ARM::t2MCR:
+ case ARM::t2MCR2:
+ case ARM::t2MCRR:
+ case ARM::t2MCRR2:
+ case ARM::t2MRC:
+ case ARM::t2MRC2:
+ case ARM::t2MRRC:
+ case ARM::t2MRRC2:
+ case ARM::t2STC2L_OFFSET:
+ case ARM::t2STC2L_OPTION:
+ case ARM::t2STC2L_POST:
+ case ARM::t2STC2L_PRE:
+ case ARM::t2STC2_OFFSET:
+ case ARM::t2STC2_OPTION:
+ case ARM::t2STC2_POST:
+ case ARM::t2STC2_PRE:
+ case ARM::t2STCL_OFFSET:
+ case ARM::t2STCL_OPTION:
+ case ARM::t2STCL_POST:
+ case ARM::t2STCL_PRE:
+ case ARM::t2STC_OFFSET:
+ case ARM::t2STC_OPTION:
+ case ARM::t2STC_POST:
+ case ARM::t2STC_PRE: {
unsigned Opcode = Inst.getOpcode();
// Inst.getOperand indexes operands in the (oops ...) and (iops ...) dags,
// CopInd is the index of the coprocessor operand.
@@ -8176,11 +8228,13 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
CopInd = 2;
else if (Opcode == ARM::t2MRC || Opcode == ARM::t2MRC2)
CopInd = 1;
- assert(Inst.getOperand(CopInd).isImm() && "Operand must be a coprocessor ID");
+ assert(Inst.getOperand(CopInd).isImm() &&
+ "Operand must be a coprocessor ID");
int64_t Coproc = Inst.getOperand(CopInd).getImm();
// Operands[2] is the coprocessor operand at syntactic level
if (ARM::isCDECoproc(Coproc, *STI))
- return Error(Operands[2]->getStartLoc(), "coprocessor must be configured as GCP");
+ return Error(Operands[2]->getStartLoc(),
+ "coprocessor must be configured as GCP");
break;
}
}
More information about the llvm-commits
mailing list