[llvm] 68400a2 - [X86] Add missing isel pattern for BLCFILL producing flags.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2020-02-17T13:20:13-08:00
New Revision: 68400a23083769244a6af07ec42ec61877a4bb12

URL: https://github.com/llvm/llvm-project/commit/68400a23083769244a6af07ec42ec61877a4bb12
DIFF: https://github.com/llvm/llvm-project/commit/68400a23083769244a6af07ec42ec61877a4bb12.diff

LOG: [X86] Add missing isel pattern for BLCFILL producing flags.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86InstrInfo.td
    llvm/test/CodeGen/X86/tbm_patterns.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
index 9bdaa74f230f..7d999c61aa1a 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -2919,6 +2919,11 @@ let Predicates = [HasTBM] in {
             (TZMSK64rr GR64:$src)>;
 
   // Patterns to match flag producing ops.
+  def : Pat<(and_flag_nocf GR32:$src, (add GR32:$src, 1)),
+            (BLCFILL32rr GR32:$src)>;
+  def : Pat<(and_flag_nocf GR64:$src, (add GR64:$src, 1)),
+            (BLCFILL64rr GR64:$src)>;
+
   def : Pat<(or_flag_nocf GR32:$src, (not (add GR32:$src, 1))),
             (BLCI32rr GR32:$src)>;
   def : Pat<(or_flag_nocf GR64:$src, (not (add GR64:$src, 1))),

diff  --git a/llvm/test/CodeGen/X86/tbm_patterns.ll b/llvm/test/CodeGen/X86/tbm_patterns.ll
index de47391acb28..4a872dbfcf9d 100644
--- a/llvm/test/CodeGen/X86/tbm_patterns.ll
+++ b/llvm/test/CodeGen/X86/tbm_patterns.ll
@@ -964,4 +964,48 @@ define i64 @tzmsk64_branch(i64 %x) nounwind {
   ret i64 %tmp3
 }
 
+define i32 @blcfill32_branch(i32 %x) nounwind {
+; CHECK-LABEL: blcfill32_branch:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    blcfilll %edi, %ebx
+; CHECK-NEXT:    jne .LBB73_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    callq bar
+; CHECK-NEXT:  .LBB73_2:
+; CHECK-NEXT:    movl %ebx, %eax
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    retq
+  %tmp2 = add i32 %x, 1
+  %tmp3 = and i32 %tmp2, %x
+  %cmp = icmp eq i32 %tmp3, 0
+  br i1 %cmp, label %1, label %2
+
+  tail call void @bar()
+  br label %2
+  ret i32 %tmp3
+}
+
+define i64 @blcfill64_branch(i64 %x) nounwind {
+; CHECK-LABEL: blcfill64_branch:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    blcfillq %rdi, %rbx
+; CHECK-NEXT:    jne .LBB74_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    callq bar
+; CHECK-NEXT:  .LBB74_2:
+; CHECK-NEXT:    movq %rbx, %rax
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    retq
+  %tmp2 = add i64 %x, 1
+  %tmp3 = and i64 %tmp2, %x
+  %cmp = icmp eq i64 %tmp3, 0
+  br i1 %cmp, label %1, label %2
+
+  tail call void @bar()
+  br label %2
+  ret i64 %tmp3
+}
+
 declare void @bar()