[PATCH] D74147: [AArch64] Add BIT/BIF support.

[Pavel Iliin via Phabricator via llvm-commits]

ilinpv marked 2 inline comments as done.
ilinpv added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:3965
+// It is expanded into BSL/BIT/BIF after register allocation.
+defm BSP : SIMDLogicalThreeVectorPseudo<TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
+defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl">;
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dmgreen wrote:
> This line it quite long. Maybe try and split it up a little like the BIC above?
Sure


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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:3988-4004
+def : Pat<(AArch64bit (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
+          (BITv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
+def : Pat<(AArch64bit (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
+          (BITv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
+def : Pat<(AArch64bit (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
+          (BITv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
+def : Pat<(AArch64bit (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
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dmgreen wrote:
> I believe that these patterns will already be included inside the SIMDLogicalThreeVectorTied BIT class, so aren't needed again here?
Yes, accidentally remained here.


Repository:
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  https://reviews.llvm.org/D74147/new/

https://reviews.llvm.org/D74147