[PATCH] D72683: [PowerPC] set instruction number as 1st priority for lsr cost model

qshanz via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Feb 10 01:53:08 PST 2020


steven.zhang added inline comments.


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Comment at: llvm/test/CodeGen/PowerPC/unal-altivec.ll:36
+; CHECK-DAG: lvsl [[MASK1:[0-9]+]], [[B1:[0-9]+]], [[C0]]
+; CHECK-DAG: add [[B3:[0-9]+]], [[B1]], [[C0]]
+; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]]
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The "add" here is new added ? Does it mean that, for this case, it produces bad code ?


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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72683/new/

https://reviews.llvm.org/D72683





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