[PATCH] D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension

[Simon Cook via Phabricator via llvm-commits]

simoncook added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCV.td:107
+// They should be added if any of the two subextension has been specified.
+def HasStdExtZbbOrZbp
+    : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">;
----------------
This isn't doing what you want it to. This patch currently causes `MC/RISCV/invalid-instruction-spellcheck.s` to fail because of the lack of an `AssemblyPredicate` so the instruction is always enabled.

Unfortunately it looks like `AsmPredicate` doesn't support saying if Feature X or Y is enabled, and we can only compose them as needing X and Y on the `Instruction` definitions themselves. I couldn't find any other backend needing something like this, so it might be that we need a dummy SubtargetFeature, or teach TableGen that AsmPredicates can be composed in an or fashion instead.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D65649/new/

https://reviews.llvm.org/D65649