[llvm] 5c6b1a6 - [TableGen] Fix spurious type error in bit assignment.
Simon Tatham via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 7 07:11:54 PST 2020
Author: Simon Tatham
Date: 2020-02-07T15:11:42Z
New Revision: 5c6b1a6dfdb428a347a25527a4aebba72cd42a3a
URL: https://github.com/llvm/llvm-project/commit/5c6b1a6dfdb428a347a25527a4aebba72cd42a3a
DIFF: https://github.com/llvm/llvm-project/commit/5c6b1a6dfdb428a347a25527a4aebba72cd42a3a.diff
LOG: [TableGen] Fix spurious type error in bit assignment.
Summary:
The following example gives the error message "expected value of type
'bits<32>', got 'bit'" on the assignment.
class Instruction { bits<32> encoding; }
def foo: Instruction { let encoding{10} = !eq(0, 1); }
But there's nothing wrong with this code: 'bit' is a perfectly good
type for the RHS of an assignment to a //single bit// of an
instruction encoding.
The problem is that `ParseBodyItem` is accidentally type-checking the
RHS against the full type of the `encoding` field, without adjusting
it in the case where we're only assigning to a subset of the bits. The
fix is trivial.
Reviewers: nhaehnle, hfinkel
Reviewed By: hfinkel
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D74220
Added:
Modified:
llvm/lib/TableGen/TGParser.cpp
llvm/test/TableGen/BitsInit.td
Removed:
################################################################################
diff --git a/llvm/lib/TableGen/TGParser.cpp b/llvm/lib/TableGen/TGParser.cpp
index 1b2809a519e3..9314523c501a 100644
--- a/llvm/lib/TableGen/TGParser.cpp
+++ b/llvm/lib/TableGen/TGParser.cpp
@@ -2640,6 +2640,11 @@ bool TGParser::ParseBodyItem(Record *CurRec) {
return TokError("Value '" + FieldName->getValue() + "' unknown!");
RecTy *Type = Field->getType();
+ if (!BitList.empty() && isa<BitsRecTy>(Type)) {
+ // When assigning to a subset of a 'bits' object, expect the RHS to have
+ // the type of that subset instead of the type of the whole object.
+ Type = BitsRecTy::get(BitList.size());
+ }
Init *Val = ParseValue(CurRec, Type);
if (!Val) return true;
diff --git a/llvm/test/TableGen/BitsInit.td b/llvm/test/TableGen/BitsInit.td
index d6d2ab12f351..16d2d07753ad 100644
--- a/llvm/test/TableGen/BitsInit.td
+++ b/llvm/test/TableGen/BitsInit.td
@@ -56,6 +56,10 @@ def {
// Make sure we can initialise ints with bits<> values.
int J = H;
int K = { 0, 1 };
+
+ bits<2> L;
+ let L{0} = 1;
+ let L{1} = !eq(L{0}, 0);
}
// CHECK: def {{.*}} {
@@ -82,4 +86,5 @@ def {
// CHECK: bits<16> I = { 0, 1, 1, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0 };
// CHECK: int J = 52275;
// CHECK: int K = 1;
+// CHECK: bits<2> L = { 0, 1 };
// CHECK: }
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