[PATCH] D74032: [DAGCombine][ARM] Combine pattern for REV16

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:5656
+                                       SelectionDAG &DAG, SDNode *N, SDValue N0,
+                                       SDValue N1, EVT VT, EVT ShiftAmountTy) {
+  if (!TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
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This looks like it only works for MVT::i32 cases, but there doesn't seem to be any VT check?


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:5662
+  ConstantSDNode *Mask1 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
+  ConstantSDNode *Mask2 = dyn_cast<ConstantSDNode>(N1.getOperand(1));
+  if (!Mask1 || !Mask2)
----------------
Use isConstOrConstSplat instead of dyn_cast<ConstantSDNode> ?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74032/new/

https://reviews.llvm.org/D74032