[PATCH] D73950: [AArch64] Make Read Write System Registers Read Only

Tue Feb 4 05:47:02 PST 2020

simon_tatham added a comment.

Mostly LGTM, except for test nitpicks.

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Comment at: llvm/test/MC/AArch64/arm64-system-encoding.s:171
 ; CHECK: msr CSSELR_EL1, x3             ; encoding: [0x03,0x00,0x1a,0xd5]
-; CHECK: msr CurrentEL, x3              ; encoding: [0x43,0x42,0x18,0xd5]
+; NOECV: :[[@LINE-94]]: error: expected writable system register or pstate
 ; CHECK: msr DACR32_EL2, x3             ; encoding: [0x03,0x30,0x1c,0xd5]
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ostannard wrote:
> The `NOECV` check prefix isn't used by any FileCheck commands.
I think it would be much more readable to move this check and the line that invoked it into their own separate section of the test file, so that the checks are right next to the input instruction.

The way you've done it in `armv8.2a-statistical-profiling.s` for `PMBIDR_EL1` and `PMSIDR_EL1` looks fine to me.

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Comment at: llvm/test/MC/AArch64/basic-a64-instructions.s:4062
 // CHECK: msr      {{daif|DAIF}}, x12                  // encoding: [0x2c,0x42,0x1b,0xd5]
-// CHECK: msr      {{CurrentEL|CURRENTEL}}, x12             // encoding: [0x4c,0x42,0x18,0xd5]
+// ERROR: :[[@LINE-254]]:6: error: expected writable system register or pstate
 // CHECK: msr      {{SPSR_irq|SPSR_IRQ}}, x12              // encoding: [0x0c,0x43,0x1c,0xd5]
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Same comment here.

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Comment at: llvm/test/MC/AArch64/gicv3-regs.s:206
 // CHECK: msr      {{ich_hcr_el2|ICH_HCR_EL2}}, x1            // encoding: [0x01,0xcb,0x1c,0xd5]
-// CHECK: msr      {{ich_misr_el2|ICH_MISR_EL2}}, x10          // encoding: [0x4a,0xcb,0x1c,0xd5]
+// ERROR: [[@LINE-54]]:13: error: expected writable system register or pstate
 // CHECK: msr      {{ich_vmcr_el2|ICH_VMCR_EL2}}, x24          // encoding: [0xf8,0xcb,0x1c,0xd5]
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And here.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D73950/new/

https://reviews.llvm.org/D73950