[PATCH] D72610: GlobalISel: Implement fewerElementsVector for G_SEXT_INREG

[Matt Arsenault via Phabricator via llvm-commits]

arsenm marked an inline comment as done.
arsenm added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir:209
     ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY [[DEF]](<2 x s32>)
-    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
     ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
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aemerson wrote:
> Why did this test change?
This is just an instruction reordering since the legalization steps now happen in a different order. Before it lowered to vector shifts before scalarizing


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  https://reviews.llvm.org/D72610/new/

https://reviews.llvm.org/D72610