[PATCH] D73534: [DebugInfo] Enable the debug entry values feature by default

[Djordje Todorovic via Phabricator via llvm-commits]

djtodoro updated this revision to Diff 241429.
djtodoro retitled this revision from "[WIP][DebugInfo] Enable the debug entry values feature by default" to "[DebugInfo] Enable the debug entry values feature by default".
djtodoro edited the summary of this revision.
djtodoro added a comment.

- Make the 'fix the asserts' as a separate patch (D73700 <https://reviews.llvm.org/D73700>)
- Leave the `llc` experimental option for targets that do not support the `CallSiteInfo` yet


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73534/new/

https://reviews.llvm.org/D73534

Files:
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Driver/CC1Options.td
  clang/lib/CodeGen/BackendUtil.cpp
  clang/lib/CodeGen/CGDebugInfo.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/test/CodeGen/debug-info-extern-call.c
  clang/test/CodeGenCXX/dbg-info-all-calls-described.cpp
  lldb/packages/Python/lldbsuite/test/decorators.py
  lldb/packages/Python/lldbsuite/test/functionalities/param_entry_vals/basic_entry_values_x86_64/Makefile
  llvm/include/llvm/Target/TargetMachine.h
  llvm/include/llvm/Target/TargetOptions.h
  llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
  llvm/lib/CodeGen/LiveDebugValues.cpp
  llvm/lib/CodeGen/MIRParser/MIRParser.cpp
  llvm/lib/CodeGen/MachineFunction.cpp
  llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMTargetMachine.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86TargetMachine.cpp
  llvm/test/CodeGen/AArch64/arm64-anyregcc.ll
  llvm/test/CodeGen/AArch64/arm64-patchpoint.ll
  llvm/test/CodeGen/AArch64/arm64-tls-dynamics.ll
  llvm/test/CodeGen/AArch64/stackmap-frame-setup.ll
  llvm/test/CodeGen/AArch64/stackmap.ll
  llvm/test/CodeGen/ARM/smml.ll
  llvm/test/CodeGen/MIR/Hexagon/bundled-call-site-info.mir
  llvm/test/CodeGen/MIR/X86/call-site-info-error1.mir
  llvm/test/CodeGen/MIR/X86/call-site-info-error2.mir
  llvm/test/CodeGen/MIR/X86/call-site-info-error3.mir
  llvm/test/CodeGen/MIR/X86/call-site-info-error4.mir
  llvm/test/CodeGen/X86/anyregcc.ll
  llvm/test/CodeGen/X86/call-site-info-output.ll
  llvm/test/CodeGen/X86/combineIncDecVector-crash.ll
  llvm/test/CodeGen/X86/deopt-bundles.ll
  llvm/test/CodeGen/X86/fast-isel-gc-intrinsics.ll
  llvm/test/CodeGen/X86/hoist-invariant-load.ll
  llvm/test/CodeGen/X86/machine-sink-and-implicit-null-checks.ll
  llvm/test/CodeGen/X86/patchpoint.ll
  llvm/test/CodeGen/X86/pr33010.ll
  llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
  llvm/test/CodeGen/X86/stackmap-fast-isel.ll
  llvm/test/CodeGen/X86/stackmap-frame-setup.ll
  llvm/test/CodeGen/X86/stackmap-large-location-size.ll
  llvm/test/CodeGen/X86/stackmap.ll
  llvm/test/CodeGen/X86/statepoint-allocas.ll
  llvm/test/CodeGen/X86/statepoint-call-lowering.ll
  llvm/test/CodeGen/X86/statepoint-forward.ll
  llvm/test/CodeGen/X86/statepoint-gctransition-call-lowering.ll
  llvm/test/CodeGen/X86/statepoint-invoke.ll
  llvm/test/CodeGen/X86/statepoint-live-in.ll
  llvm/test/CodeGen/X86/statepoint-no-realign-stack.ll
  llvm/test/CodeGen/X86/statepoint-stackmap-format.ll
  llvm/test/CodeGen/X86/statepoint-uniqueing.ll
  llvm/test/CodeGen/X86/statepoint-vector-bad-spill.ll
  llvm/test/CodeGen/X86/statepoint-vector.ll
  llvm/test/CodeGen/X86/xray-custom-log.ll
  llvm/test/CodeGen/X86/xray-typed-event-log.ll
  llvm/test/DebugInfo/AArch64/call-site-info-output.ll
  llvm/test/DebugInfo/ARM/call-site-info-output.ll
  llvm/test/DebugInfo/ARM/entry-value-multi-byte-expr.ll
  llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpret-movzxi.mir
  llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir
  llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir
  llvm/test/DebugInfo/MIR/ARM/dbgcall-site-interpretation.mir
  llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir
  llvm/test/DebugInfo/MIR/ARM/if-coverter-call-site-info.mir
  llvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir
  llvm/test/DebugInfo/MIR/Hexagon/live-debug-values-bundled-entry-values.mir
  llvm/test/DebugInfo/MIR/SystemZ/call-site-lzer.mir
  llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir
  llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir
  llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir
  llvm/test/DebugInfo/MIR/X86/dbgcall-site-copy-super-sub.mir
  llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir
  llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir
  llvm/test/DebugInfo/MIR/X86/dbgcall-site-partial-describe.mir
  llvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir
  llvm/test/DebugInfo/MIR/X86/dbgcall-site-reg-shuffle.mir
  llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir
  llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir
  llvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir
  llvm/test/DebugInfo/MIR/X86/entry-value-of-modified-param.mir
  llvm/test/DebugInfo/MIR/X86/entry-values-diamond-bbs.mir
  llvm/test/DebugInfo/MIR/X86/kill-entry-value-after-diamond-bbs.mir
  llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir
  llvm/test/DebugInfo/MIR/X86/propagate-entry-value-cross-bbs.mir
  llvm/test/DebugInfo/MIR/X86/unreachable-block-call-site.mir
  llvm/test/DebugInfo/Sparc/entry-value-complex-reg-expr.ll
  llvm/test/DebugInfo/X86/dbg-value-range.ll
  llvm/test/DebugInfo/X86/dbg-value-regmask-clobber.ll
  llvm/test/DebugInfo/X86/dbgcall-site-64-bit-imms.ll
  llvm/test/DebugInfo/X86/dbgcall-site-zero-valued-imms.ll
  llvm/test/DebugInfo/X86/loclists-dwp.ll
  llvm/test/tools/llvm-dwarfdump/X86/locstats.ll
  llvm/test/tools/llvm-dwarfdump/X86/stats-dbg-callsite-info.ll
  llvm/test/tools/llvm-dwarfdump/X86/valid-call-site-GNU-extensions.ll
  llvm/test/tools/llvm-locstats/locstats.ll

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