[llvm] f717483 - GlobalISel: Assert on invalid bitcast in MIRBuilder

Matt Arsenault via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 29 07:49:50 PST 2020


Author: Matt Arsenault
Date: 2020-01-29T07:49:39-08:00
New Revision: f717483acd5e7d278ecd54ae80d2c1138fb51d06

URL: https://github.com/llvm/llvm-project/commit/f717483acd5e7d278ecd54ae80d2c1138fb51d06
DIFF: https://github.com/llvm/llvm-project/commit/f717483acd5e7d278ecd54ae80d2c1138fb51d06.diff

LOG: GlobalISel: Assert on invalid bitcast in MIRBuilder

The other casts validate, so this should too.

Added: 
    

Modified: 
    llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 950044730cd6..841342b6e3b7 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -1013,6 +1013,13 @@ MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
                      SrcOps[0].getLLTTy(*getMRI()), false);
     break;
   }
+  case TargetOpcode::G_BITCAST: {
+    assert(DstOps.size() == 1 && "Invalid Dst");
+    assert(SrcOps.size() == 1 && "Invalid Srcs");
+    assert(DstOps[0].getLLTTy(*getMRI()).getSizeInBits() ==
+           SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() && "invalid bitcast");
+    break;
+  }
   case TargetOpcode::COPY:
     assert(DstOps.size() == 1 && "Invalid Dst");
     // If the caller wants to add a subreg source it has to be done separately


        


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