[llvm] 752e2e2 - AMDGPU/GlobalISel: Rewrite fadd select tests
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 29 07:49:49 PST 2020
Author: Matt Arsenault
Date: 2020-01-29T07:49:38-08:00
New Revision: 752e2e245ab6bfb6203c226bbe295ddf4e018830
URL: https://github.com/llvm/llvm-project/commit/752e2e245ab6bfb6203c226bbe295ddf4e018830
DIFF: https://github.com/llvm/llvm-project/commit/752e2e245ab6bfb6203c226bbe295ddf4e018830.diff
LOG: AMDGPU/GlobalISel: Rewrite fadd select tests
Convert to the style most others use with one test instruction per
function, and use an implicit use to ensure the result register class
is constrained.
Change-Id: I6109148b0e3c80aa5535796a37abca583c19a936
Added:
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir
Modified:
Removed:
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir
deleted file mode 100644
index a1c67eeef0bd..000000000000
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir
+++ /dev/null
@@ -1,33 +0,0 @@
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
-
----
-
-name: fadd
-legalized: true
-regBankSelected: true
-
-# GCN-LABEL: name: fadd
-body: |
- bb.0:
- liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4
- %0:sgpr(s32) = COPY $sgpr0
- %1:vgpr(s32) = COPY $vgpr0
- %2:vgpr(s32) = COPY $vgpr1
- %3:vgpr(p1) = COPY $vgpr3_vgpr4
-
- ; fadd vs
- ; GCN: V_ADD_F32_e64
- %4:vgpr(s32) = G_FADD %1, %0
-
- ; fadd sv
- ; GCN: V_ADD_F32_e64
- %5:vgpr(s32) = G_FADD %0, %1
-
- ; fadd vv
- ; GCN: V_ADD_F32_e64
- %6:vgpr(s32) = G_FADD %1, %2
-
- G_STORE %4, %3 :: (store 4, addrspace 1)
- G_STORE %5, %3 :: (store 4, addrspace 1)
- G_STORE %6, %3 :: (store 4, addrspace 1)
-...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir
new file mode 100644
index 000000000000..c94e0665da35
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir
@@ -0,0 +1,193 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
+
+---
+
+name: fadd_s16_vvv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; GFX8-LABEL: name: fadd_s16_vvv
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vgpr(s16) = G_FADD %2, %3
+ S_ENDPGM 0, implicit %4
+
+...
+
+---
+
+name: fadd_s16_vsv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $sgpr0
+ ; GFX8-LABEL: name: fadd_s16_vsv
+ ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:vgpr(s32) = COPY $vgpr0
+ %2:sgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vgpr(s16) = G_FADD %2, %3
+ S_ENDPGM 0, implicit %4
+
+...
+
+---
+
+name: fadd_s16_vvs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $sgpr0
+ ; GFX8-LABEL: name: fadd_s16_vvs
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:sgpr(s32) = COPY $sgpr0
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:sgpr(s16) = G_TRUNC %1
+ %4:vgpr(s16) = G_FADD %2, %3
+ S_ENDPGM 0, implicit %4
+
+...
+
+---
+
+name: fadd_s16_vvv_fabs_lhs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; GFX8-LABEL: name: fadd_s16_vvv_fabs_lhs
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vgpr(s16) = G_FABS %2
+ %5:vgpr(s16) = G_FADD %4, %3
+ S_ENDPGM 0, implicit %5
+
+...
+
+---
+
+name: fadd_s16_vvv_fabs_rhs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; GFX8-LABEL: name: fadd_s16_vvv_fabs_rhs
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 2, [[COPY1]], 0, 0, implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vgpr(s16) = G_FABS %3
+ %5:vgpr(s16) = G_FADD %2, %4
+ S_ENDPGM 0, implicit %5
+
+...
+
+---
+
+name: fadd_s16_vvv_fneg_fabs_lhs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; GFX8-LABEL: name: fadd_s16_vvv_fneg_fabs_lhs
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vgpr(s16) = G_FABS %2
+ %5:vgpr(s16) = G_FNEG %4
+ %6:vgpr(s16) = G_FADD %5, %3
+ S_ENDPGM 0, implicit %6
+
+...
+
+---
+
+name: fadd_s16_vvv_fneg_fabs_rhs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; GFX8-LABEL: name: fadd_s16_vvv_fneg_fabs_rhs
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 3, [[COPY1]], 0, 0, implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_TRUNC %1
+ %4:vgpr(s16) = G_FABS %3
+ %5:vgpr(s16) = G_FNEG %4
+ %6:vgpr(s16) = G_FADD %2, %5
+ S_ENDPGM 0, implicit %6
+
+...
+
+---
+
+name: fadd_s16_fneg_copy_sgpr
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $sgpr0
+ ; GFX8-LABEL: name: fadd_s16_fneg_copy_sgpr
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:sgpr(s32) = COPY $sgpr0
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:sgpr(s16) = G_TRUNC %1
+ %4:sgpr(s16) = G_FNEG %3
+ %5:vgpr(s16) = G_FADD %2, %4
+ S_ENDPGM 0, implicit %5
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir
new file mode 100644
index 000000000000..833191517b12
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir
@@ -0,0 +1,211 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
+
+---
+
+name: fadd_s32_vvv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; GFX6-LABEL: name: fadd_s32_vvv
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = G_FADD %0, %1
+ S_ENDPGM 0, implicit %2
+
+...
+
+---
+
+name: fadd_s32_vsv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $sgpr0
+ ; GFX6-LABEL: name: fadd_s32_vsv
+ ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:vgpr(s32) = COPY $vgpr0
+ %2:vgpr(s32) = G_FADD %0, %1
+ S_ENDPGM 0, implicit %2
+
+...
+
+---
+
+name: fadd_s32_vvs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $sgpr0
+ ; GFX6-LABEL: name: fadd_s32_vvs
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:sgpr(s32) = COPY $sgpr0
+ %2:vgpr(s32) = G_FADD %0, %1
+ S_ENDPGM 0, implicit %2
+
+...
+
+---
+
+name: fadd_s32_vvv_fabs_lhs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; GFX6-LABEL: name: fadd_s32_vvv_fabs_lhs
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = G_FABS %0
+ %3:vgpr(s32) = G_FADD %2, %1
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+
+name: fadd_s32_vvv_fabs_rhs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; GFX6-LABEL: name: fadd_s32_vvv_fabs_rhs
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 2, [[COPY]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = G_FABS %1
+ %3:vgpr(s32) = G_FADD %1, %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+
+name: fadd_s32_vvv_fneg_fabs_lhs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; GFX6-LABEL: name: fadd_s32_vvv_fneg_fabs_lhs
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = G_FABS %0
+ %3:vgpr(s32) = G_FNEG %2
+ %4:vgpr(s32) = G_FADD %3, %1
+ S_ENDPGM 0, implicit %4
+
+...
+
+---
+
+name: fadd_s32_vvv_fneg_fabs_rhs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; GFX6-LABEL: name: fadd_s32_vvv_fneg_fabs_rhs
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 3, [[COPY]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = G_FABS %1
+ %3:vgpr(s32) = G_FNEG %2
+ %4:vgpr(s32) = G_FADD %1, %3
+ S_ENDPGM 0, implicit %4
+
+...
+
+# Need to look through reg bank copy to find source modifiers
+---
+
+name: fadd_s32_fneg_copy_sgpr
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $sgpr0
+ ; GFX6-LABEL: name: fadd_s32_fneg_copy_sgpr
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
+ ; GFX6: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
+ ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_XOR_B32_]]
+ ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY2]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:sgpr(s32) = COPY $sgpr0
+ %2:sgpr(s32) = G_FNEG %1
+ %3:vgpr(s32) = COPY %2
+ %4:vgpr(s32) = G_FADD %0, %3
+ S_ENDPGM 0, implicit %4
+
+...
+
+# Need to look through copy in between fneg and fabs
+
+---
+
+name: fadd_s32_copy_fneg_copy_fabs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $sgpr0
+ ; GFX6-LABEL: name: fadd_s32_copy_fneg_copy_fabs
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
+ ; GFX6: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
+ ; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
+ ; GFX6: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[S_AND_B32_]], [[S_MOV_B32_1]], implicit-def $scc
+ ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[S_XOR_B32_]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:sgpr(s32) = COPY $sgpr0
+ %2:sgpr(s32) = G_FABS %1
+ %3:sgpr(s32) = COPY %2
+ %4:sgpr(s32) = G_FNEG %3
+ %5:sgpr(s32) = COPY %4
+ %6:vgpr(s32) = G_FADD %0, %5
+ S_ENDPGM 0, implicit %6
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir
new file mode 100644
index 000000000000..1e8b5c2ad8f2
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir
@@ -0,0 +1,184 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
+
+---
+
+name: fadd_s64_vvv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; GFX6-LABEL: name: fadd_s64_vvv
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vgpr(s64) = G_FADD %0, %1
+ S_ENDPGM 0, implicit %2
+
+...
+
+---
+
+name: fadd_s64_vsv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
+ ; GFX6-LABEL: name: fadd_s64_vsv
+ ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
+ %0:sgpr(s64) = COPY $sgpr0_sgpr1
+ %1:vgpr(s64) = COPY $vgpr0_vgpr1
+ %2:vgpr(s64) = G_FADD %0, %1
+ S_ENDPGM 0, implicit %2
+
+...
+
+---
+
+name: fadd_s64_vvs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
+ ; GFX6-LABEL: name: fadd_s64_vvs
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:sgpr(s64) = COPY $sgpr0_sgpr1
+ %2:vgpr(s64) = G_FADD %0, %1
+ S_ENDPGM 0, implicit %2
+
+...
+
+---
+
+name: fadd_s64_vvv_fabs_lhs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; GFX6-LABEL: name: fadd_s64_vvv_fabs_lhs
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vgpr(s64) = G_FABS %0
+ %3:vgpr(s64) = G_FADD %2, %1
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+
+name: fadd_s64_vvv_fabs_rhs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; GFX6-LABEL: name: fadd_s64_vvv_fabs_rhs
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 2, [[COPY]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vgpr(s64) = G_FABS %1
+ %3:vgpr(s64) = G_FADD %1, %2
+ S_ENDPGM 0, implicit %3
+
+...
+
+---
+
+name: fadd_s64_vvv_fneg_fabs_lhs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; GFX6-LABEL: name: fadd_s64_vvv_fneg_fabs_lhs
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
+ ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr2_vgpr3
+ %2:vgpr(s64) = G_FABS %0
+ %3:vgpr(s64) = G_FNEG %2
+ %4:vgpr(s64) = G_FADD %3, %1
+ S_ENDPGM 0, implicit %4
+
+...
+
+---
+
+name: fadd_s64_vvv_fneg_fabs_rhs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+ ; GFX6-LABEL: name: fadd_s64_vvv_fneg_fabs_rhs
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 3, [[COPY]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s64) = COPY $vgpr0_vgpr1
+ %2:vgpr(s64) = G_FABS %1
+ %3:vgpr(s64) = G_FNEG %2
+ %4:vgpr(s64) = G_FADD %1, %3
+ S_ENDPGM 0, implicit %4
+
+...
+
+# Need to look through reg bank copy to find source modifiers
+
+---
+
+name: fadd_s64_fneg_copy_sgpr
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
+ ; GFX6-LABEL: name: fadd_s64_fneg_copy_sgpr
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub0
+ ; GFX6: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub1
+ ; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
+ ; GFX6: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY3]], [[S_MOV_B32_]], implicit-def $scc
+ ; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[S_XOR_B32_]], %subreg.sub1
+ ; GFX6: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]]
+ ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 0, [[COPY4]], 0, 0, implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:sgpr(s64) = COPY $sgpr0_sgpr1
+ %2:sgpr(s64) = G_FNEG %1
+ %3:vgpr(s64) = COPY %2
+ %4:vgpr(s64) = G_FADD %0, %3
+ S_ENDPGM 0, implicit %4
+
+...
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